diff options
| author | Dave Airlie <airlied@redhat.com> | 2016-01-11 11:48:18 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2016-01-11 11:48:18 +1000 |
| commit | 57b4f7e68720e8a9f5e6e9e61446ec36822e4c57 (patch) | |
| tree | e6143801b0e29d132695b8056872a4e56f5a699c /drivers/gpu | |
| parent | b483666bb4939ee14501da9978e5f87e4aa22228 (diff) | |
| parent | a18c91decee6ba4fc252bf82108adc1207dd1f86 (diff) | |
| download | linux-57b4f7e68720e8a9f5e6e9e61446ec36822e4c57.tar.bz2 | |
Merge branch 'linux-4.5' of git://github.com/skeggsb/linux into drm-next
- gk20a instmem fixes / improvements
- more gm10x vs gm20x differences deal with
- better support for high-frequency hdmi modes
- pstate control interfaces moved to debugfs
- support for pcie link speed changes
- misc other fixes across the board
* 'linux-4.5' of git://github.com/skeggsb/linux: (50 commits)
drm/nouveau/pmu: prevent falcon from acking interrupts routed to the host
drm/nouveau/perf: change pcie speed on pstate change
drm/nouveau/perf: add fields for pci speed and width and use it for the pstates
drm/nouveau/bios/perf: parse the pci speed from the bios for tesla and newer cards
drm/nouveau/pci: implement pcie speed change for kepler+
drm/nouveau/pci: implement pcie speed change for Fermi
drm/nouveau/pci: implement pcie speed change for tesla
drm/nouveau/pci: implement generic code for pcie speed change
drm/nouveau/pci: add gk104 variant
drm/nouveau/pci: add gf106 variant
drm/nouveau/kms: take mode_config mutex in connector hotplug path
drm/nouveau/nouveau/perfmon: add interface files for current core voltage
drm/nouveau/sysfs: remove pstate interface
drm/nouveau/debugfs: add copy of sysfs pstate interface ported to debugfs
drm/nouveau/debugfs: we need a ctrl object for debugfs
drm/nouveau/debugfs: rename functions to indicate they are used inside drm
drm/nouveau/debugfs: add infrastructure to add files with other fops than only read
drm/nouveau/fifo/gf100: remove references to "daemon"
drm/nouveau/fb/nv50: remove references to "daemon"
drm/nouveau/clk: remove references to "daemon"
...
Diffstat (limited to 'drivers/gpu')
141 files changed, 4879 insertions, 3704 deletions
diff --git a/drivers/gpu/drm/nouveau/Kbuild b/drivers/gpu/drm/nouveau/Kbuild index a34b437dbc8f..2527bf4ca5d9 100644 --- a/drivers/gpu/drm/nouveau/Kbuild +++ b/drivers/gpu/drm/nouveau/Kbuild @@ -24,7 +24,6 @@ nouveau-y += nouveau_hwmon.o nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o nouveau-y += nouveau_nvif.o nouveau-$(CONFIG_NOUVEAU_PLATFORM_DRIVER) += nouveau_platform.o -nouveau-y += nouveau_sysfs.o nouveau-y += nouveau_usif.o # userspace <-> nvif nouveau-y += nouveau_vga.o diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0002.h b/drivers/gpu/drm/nouveau/include/nvif/cl0002.h new file mode 100644 index 000000000000..6d72ed38da32 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0002.h @@ -0,0 +1,66 @@ +#ifndef __NVIF_CL0002_H__ +#define __NVIF_CL0002_H__ + +struct nv_dma_v0 { + __u8 version; +#define NV_DMA_V0_TARGET_VM 0x00 +#define NV_DMA_V0_TARGET_VRAM 0x01 +#define NV_DMA_V0_TARGET_PCI 0x02 +#define NV_DMA_V0_TARGET_PCI_US 0x03 +#define NV_DMA_V0_TARGET_AGP 0x04 + __u8 target; +#define NV_DMA_V0_ACCESS_VM 0x00 +#define NV_DMA_V0_ACCESS_RD 0x01 +#define NV_DMA_V0_ACCESS_WR 0x02 +#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) + __u8 access; + __u8 pad03[5]; + __u64 start; + __u64 limit; + /* ... chipset-specific class data */ +}; + +struct nv50_dma_v0 { + __u8 version; +#define NV50_DMA_V0_PRIV_VM 0x00 +#define NV50_DMA_V0_PRIV_US 0x01 +#define NV50_DMA_V0_PRIV__S 0x02 + __u8 priv; +#define NV50_DMA_V0_PART_VM 0x00 +#define NV50_DMA_V0_PART_256 0x01 +#define NV50_DMA_V0_PART_1KB 0x02 + __u8 part; +#define NV50_DMA_V0_COMP_NONE 0x00 +#define NV50_DMA_V0_COMP_1 0x01 +#define NV50_DMA_V0_COMP_2 0x02 +#define NV50_DMA_V0_COMP_VM 0x03 + __u8 comp; +#define NV50_DMA_V0_KIND_PITCH 0x00 +#define NV50_DMA_V0_KIND_VM 0x7f + __u8 kind; + __u8 pad05[3]; +}; + +struct gf100_dma_v0 { + __u8 version; +#define GF100_DMA_V0_PRIV_VM 0x00 +#define GF100_DMA_V0_PRIV_US 0x01 +#define GF100_DMA_V0_PRIV__S 0x02 + __u8 priv; +#define GF100_DMA_V0_KIND_PITCH 0x00 +#define GF100_DMA_V0_KIND_VM 0xff + __u8 kind; + __u8 pad03[5]; +}; + +struct gf119_dma_v0 { + __u8 version; +#define GF119_DMA_V0_PAGE_LP 0x00 +#define GF119_DMA_V0_PAGE_SP 0x01 + __u8 page; +#define GF119_DMA_V0_KIND_PITCH 0x00 +#define GF119_DMA_V0_KIND_VM 0xff + __u8 kind; + __u8 pad03[5]; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0046.h b/drivers/gpu/drm/nouveau/include/nvif/cl0046.h new file mode 100644 index 000000000000..a6a71f4ad91e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0046.h @@ -0,0 +1,28 @@ +#ifndef __NVIF_CL0046_H__ +#define __NVIF_CL0046_H__ + +#define NV04_DISP_NTFY_VBLANK 0x00 +#define NV04_DISP_NTFY_CONN 0x01 + +struct nv04_disp_mthd_v0 { + __u8 version; +#define NV04_DISP_SCANOUTPOS 0x00 + __u8 method; + __u8 head; + __u8 pad03[5]; +}; + +struct nv04_disp_scanoutpos_v0 { + __u8 version; + __u8 pad01[7]; + __s64 time[2]; + __u16 vblanks; + __u16 vblanke; + __u16 vtotal; + __u16 vline; + __u16 hblanks; + __u16 hblanke; + __u16 htotal; + __u16 hline; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl006b.h b/drivers/gpu/drm/nouveau/include/nvif/cl006b.h new file mode 100644 index 000000000000..309ab8a3d9e8 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl006b.h @@ -0,0 +1,11 @@ +#ifndef __NVIF_CL006B_H__ +#define __NVIF_CL006B_H__ + +struct nv03_channel_dma_v0 { + __u8 version; + __u8 chid; + __u8 pad02[2]; + __u32 offset; + __u64 pushbuf; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h new file mode 100644 index 000000000000..331620a52afa --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h @@ -0,0 +1,45 @@ +#ifndef __NVIF_CL0080_H__ +#define __NVIF_CL0080_H__ + +struct nv_device_v0 { + __u8 version; + __u8 pad01[7]; + __u64 device; /* device identifier, ~0 for client default */ +}; + +#define NV_DEVICE_V0_INFO 0x00 +#define NV_DEVICE_V0_TIME 0x01 + +struct nv_device_info_v0 { + __u8 version; +#define NV_DEVICE_INFO_V0_IGP 0x00 +#define NV_DEVICE_INFO_V0_PCI 0x01 +#define NV_DEVICE_INFO_V0_AGP 0x02 +#define NV_DEVICE_INFO_V0_PCIE 0x03 +#define NV_DEVICE_INFO_V0_SOC 0x04 + __u8 platform; + __u16 chipset; /* from NV_PMC_BOOT_0 */ + __u8 revision; /* from NV_PMC_BOOT_0 */ +#define NV_DEVICE_INFO_V0_TNT 0x01 +#define NV_DEVICE_INFO_V0_CELSIUS 0x02 +#define NV_DEVICE_INFO_V0_KELVIN 0x03 +#define NV_DEVICE_INFO_V0_RANKINE 0x04 +#define NV_DEVICE_INFO_V0_CURIE 0x05 +#define NV_DEVICE_INFO_V0_TESLA 0x06 +#define NV_DEVICE_INFO_V0_FERMI 0x07 +#define NV_DEVICE_INFO_V0_KEPLER 0x08 +#define NV_DEVICE_INFO_V0_MAXWELL 0x09 + __u8 family; + __u8 pad06[2]; + __u64 ram_size; + __u64 ram_user; + char chip[16]; + char name[64]; +}; + +struct nv_device_time_v0 { + __u8 version; + __u8 pad01[7]; + __u64 time; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl506e.h b/drivers/gpu/drm/nouveau/include/nvif/cl506e.h new file mode 100644 index 000000000000..aa94b8cf9679 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl506e.h @@ -0,0 +1,12 @@ +#ifndef __NVIF_CL506E_H__ +#define __NVIF_CL506E_H__ + +struct nv50_channel_dma_v0 { + __u8 version; + __u8 chid; + __u8 pad02[6]; + __u64 vm; + __u64 pushbuf; + __u64 offset; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl506f.h b/drivers/gpu/drm/nouveau/include/nvif/cl506f.h new file mode 100644 index 000000000000..3b7101966de4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl506f.h @@ -0,0 +1,13 @@ +#ifndef __NVIF_CL506F_H__ +#define __NVIF_CL506F_H__ + +struct nv50_channel_gpfifo_v0 { + __u8 version; + __u8 chid; + __u8 pad02[2]; + __u32 ilength; + __u64 ioffset; + __u64 pushbuf; + __u64 vm; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h new file mode 100644 index 000000000000..d15c296b5f33 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h @@ -0,0 +1,99 @@ +#ifndef __NVIF_CL5070_H__ +#define __NVIF_CL5070_H__ + +#define NV50_DISP_MTHD 0x00 + +struct nv50_disp_mthd_v0 { + __u8 version; +#define NV50_DISP_SCANOUTPOS 0x00 + __u8 method; + __u8 head; + __u8 pad03[5]; +}; + +struct nv50_disp_scanoutpos_v0 { + __u8 version; + __u8 pad01[7]; + __s64 time[2]; + __u16 vblanks; + __u16 vblanke; + __u16 vtotal; + __u16 vline; + __u16 hblanks; + __u16 hblanke; + __u16 htotal; + __u16 hline; +}; + +struct nv50_disp_mthd_v1 { + __u8 version; +#define NV50_DISP_MTHD_V1_DAC_PWR 0x10 +#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 +#define NV50_DISP_MTHD_V1_SOR_PWR 0x20 +#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 +#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 +#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 +#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 +#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 + __u8 method; + __u16 hasht; + __u16 hashm; + __u8 pad06[2]; +}; + +struct nv50_disp_dac_pwr_v0 { + __u8 version; + __u8 state; + __u8 data; + __u8 vsync; + __u8 hsync; + __u8 pad05[3]; +}; + +struct nv50_disp_dac_load_v0 { + __u8 version; + __u8 load; + __u8 pad02[2]; + __u32 data; +}; + +struct nv50_disp_sor_pwr_v0 { + __u8 version; + __u8 state; + __u8 pad02[6]; +}; + +struct nv50_disp_sor_hda_eld_v0 { + __u8 version; + __u8 pad01[7]; + __u8 data[]; +}; + +struct nv50_disp_sor_hdmi_pwr_v0 { + __u8 version; + __u8 state; + __u8 max_ac_packet; + __u8 rekey; + __u8 pad04[4]; +}; + +struct nv50_disp_sor_lvds_script_v0 { + __u8 version; + __u8 pad01[1]; + __u16 script; + __u8 pad04[4]; +}; + +struct nv50_disp_sor_dp_pwr_v0 { + __u8 version; + __u8 state; + __u8 pad02[6]; +}; + +struct nv50_disp_pior_pwr_v0 { + __u8 version; + __u8 state; + __u8 type; + __u8 pad03[5]; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507a.h b/drivers/gpu/drm/nouveau/include/nvif/cl507a.h new file mode 100644 index 000000000000..12e0643b78bd --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507a.h @@ -0,0 +1,11 @@ +#ifndef __NVIF_CL507A_H__ +#define __NVIF_CL507A_H__ + +struct nv50_disp_cursor_v0 { + __u8 version; + __u8 head; + __u8 pad02[6]; +}; + +#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507b.h b/drivers/gpu/drm/nouveau/include/nvif/cl507b.h new file mode 100644 index 000000000000..99e9d8c47f60 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507b.h @@ -0,0 +1,11 @@ +#ifndef __NVIF_CL507B_H__ +#define __NVIF_CL507B_H__ + +struct nv50_disp_overlay_v0 { + __u8 version; + __u8 head; + __u8 pad02[6]; +}; + +#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507c.h b/drivers/gpu/drm/nouveau/include/nvif/cl507c.h new file mode 100644 index 000000000000..6af70dbdfd9f --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507c.h @@ -0,0 +1,12 @@ +#ifndef __NVIF_CL507C_H__ +#define __NVIF_CL507C_H__ + +struct nv50_disp_base_channel_dma_v0 { + __u8 version; + __u8 head; + __u8 pad02[6]; + __u64 pushbuf; +}; + +#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507d.h b/drivers/gpu/drm/nouveau/include/nvif/cl507d.h new file mode 100644 index 000000000000..5ab0c9e4c6a3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507d.h @@ -0,0 +1,11 @@ +#ifndef __NVIF_CL507D_H__ +#define __NVIF_CL507D_H__ + +struct nv50_disp_core_channel_dma_v0 { + __u8 version; + __u8 pad01[7]; + __u64 pushbuf; +}; + +#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507e.h b/drivers/gpu/drm/nouveau/include/nvif/cl507e.h new file mode 100644 index 000000000000..c06209f3cac4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl507e.h @@ -0,0 +1,12 @@ +#ifndef __NVIF_CL507E_H__ +#define __NVIF_CL507E_H__ + +struct nv50_disp_overlay_channel_dma_v0 { + __u8 version; + __u8 head; + __u8 pad02[6]; + __u64 pushbuf; +}; + +#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826e.h b/drivers/gpu/drm/nouveau/include/nvif/cl826e.h new file mode 100644 index 000000000000..05e6ef7cd190 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl826e.h @@ -0,0 +1,14 @@ +#ifndef __NVIF_CL826E_H__ +#define __NVIF_CL826E_H__ + +struct g82_channel_dma_v0 { + __u8 version; + __u8 chid; + __u8 pad02[6]; + __u64 vm; + __u64 pushbuf; + __u64 offset; +}; + +#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826f.h b/drivers/gpu/drm/nouveau/include/nvif/cl826f.h new file mode 100644 index 000000000000..cecafcb1e954 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl826f.h @@ -0,0 +1,15 @@ +#ifndef __NVIF_CL826F_H__ +#define __NVIF_CL826F_H__ + +struct g82_channel_gpfifo_v0 { + __u8 version; + __u8 chid; + __u8 pad02[2]; + __u32 ilength; + __u64 ioffset; + __u64 pushbuf; + __u64 vm; +}; + +#define G82_CHANNEL_GPFIFO_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h new file mode 100644 index 000000000000..2caf0838fcfd --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h @@ -0,0 +1,14 @@ +#ifndef __NVIF_CL906F_H__ +#define __NVIF_CL906F_H__ + +struct fermi_channel_gpfifo_v0 { + __u8 version; + __u8 chid; + __u8 pad02[2]; + __u32 ilength; + __u64 ioffset; + __u64 vm; +}; + +#define FERMI_CHANNEL_GPFIFO_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl9097.h b/drivers/gpu/drm/nouveau/include/nvif/cl9097.h new file mode 100644 index 000000000000..4057676d2981 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cl9097.h @@ -0,0 +1,44 @@ +#ifndef __NVIF_CL9097_H__ +#define __NVIF_CL9097_H__ + +#define FERMI_A_ZBC_COLOR 0x00 +#define FERMI_A_ZBC_DEPTH 0x01 + +struct fermi_a_zbc_color_v0 { + __u8 version; +#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 +#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 +#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 +#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 +#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c +#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 +#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 +#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 +#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 +#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c +#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 +#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 +#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 +#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c +#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 +#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 +#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 +#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c +#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 + __u8 format; + __u8 index; + __u8 pad03[5]; + __u32 ds[4]; + __u32 l2[4]; +}; + +struct fermi_a_zbc_depth_v0 { + __u8 version; +#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 + __u8 format; + __u8 index; + __u8 pad03[5]; + __u32 ds; + __u32 l2; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h new file mode 100644 index 000000000000..85b7827eb782 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h @@ -0,0 +1,21 @@ +#ifndef __NVIF_CLA06F_H__ +#define __NVIF_CLA06F_H__ + +struct kepler_channel_gpfifo_a_v0 { + __u8 version; +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 + __u8 engine; + __u16 chid; + __u32 ilength; + __u64 ioffset; + __u64 vm; +}; + +#define KEPLER_CHANNEL_GPFIFO_A_V0_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 95a64d89547c..4179cd65ac0a 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -1,16 +1,21 @@ #ifndef __NVIF_CLASS_H__ #define __NVIF_CLASS_H__ -/******************************************************************************* - * class identifiers - ******************************************************************************/ +/* these class numbers are made up by us, and not nvidia-assigned */ +#define NVIF_CLASS_CONTROL /* if0001.h */ -1 +#define NVIF_CLASS_PERFMON /* if0002.h */ -2 +#define NVIF_CLASS_PERFDOM /* if0003.h */ -3 +#define NVIF_CLASS_SW_NV04 /* if0004.h */ -4 +#define NVIF_CLASS_SW_NV10 /* if0005.h */ -5 +#define NVIF_CLASS_SW_NV50 /* if0005.h */ -6 +#define NVIF_CLASS_SW_GF100 /* if0005.h */ -7 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ -#define NV_DEVICE 0x00000080 +#define NV_DEVICE /* cl0080.h */ 0x00000080 -#define NV_DMA_FROM_MEMORY 0x00000002 -#define NV_DMA_TO_MEMORY 0x00000003 -#define NV_DMA_IN_MEMORY 0x0000003d +#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 +#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 +#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d #define FERMI_TWOD_A 0x0000902d @@ -19,85 +24,85 @@ #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 -#define NV04_DISP 0x00000046 - -#define NV03_CHANNEL_DMA 0x0000006b -#define NV10_CHANNEL_DMA 0x0000006e -#define NV17_CHANNEL_DMA 0x0000176e -#define NV40_CHANNEL_DMA 0x0000406e -#define NV50_CHANNEL_DMA 0x0000506e -#define G82_CHANNEL_DMA 0x0000826e - -#define NV50_CHANNEL_GPFIFO 0x0000506f -#define G82_CHANNEL_GPFIFO 0x0000826f -#define FERMI_CHANNEL_GPFIFO 0x0000906f -#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f -#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f - -#define NV50_DISP 0x00005070 -#define G82_DISP 0x00008270 -#define GT200_DISP 0x00008370 -#define GT214_DISP 0x00008570 -#define GT206_DISP 0x00008870 -#define GF110_DISP 0x00009070 -#define GK104_DISP 0x00009170 -#define GK110_DISP 0x00009270 -#define GM107_DISP 0x00009470 -#define GM204_DISP 0x00009570 +#define NV04_DISP /* cl0046.h */ 0x00000046 + +#define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b +#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e +#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e +#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e +#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e +#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e + +#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f +#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f +#define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f +#define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f +#define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f + +#define NV50_DISP /* cl5070.h */ 0x00005070 +#define G82_DISP /* cl5070.h */ 0x00008270 +#define GT200_DISP /* cl5070.h */ 0x00008370 +#define GT214_DISP /* cl5070.h */ 0x00008570 +#define GT206_DISP /* cl5070.h */ 0x00008870 +#define GF110_DISP /* cl5070.h */ 0x00009070 +#define GK104_DISP /* cl5070.h */ 0x00009170 +#define GK110_DISP /* cl5070.h */ 0x00009270 +#define GM107_DISP /* cl5070.h */ 0x00009470 +#define GM204_DISP /* cl5070.h */ 0x00009570 #define NV31_MPEG 0x00003174 #define G82_MPEG 0x00008274 #define NV74_VP2 0x00007476 -#define NV50_DISP_CURSOR 0x0000507a -#define G82_DISP_CURSOR 0x0000827a -#define GT214_DISP_CURSOR 0x0000857a -#define GF110_DISP_CURSOR 0x0000907a -#define GK104_DISP_CURSOR 0x0000917a - -#define NV50_DISP_OVERLAY 0x0000507b -#define G82_DISP_OVERLAY 0x0000827b -#define GT214_DISP_OVERLAY 0x0000857b -#define GF110_DISP_OVERLAY 0x0000907b -#define GK104_DISP_OVERLAY 0x0000917b - -#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c -#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c -#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c -#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c -#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c -#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c -#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c - -#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d -#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d -#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d -#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d -#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d -#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d -#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d -#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d -#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d -#define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d - -#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e -#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e -#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e -#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e -#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e -#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e - -#define FERMI_A 0x00009097 -#define FERMI_B 0x00009197 -#define FERMI_C 0x00009297 - -#define KEPLER_A 0x0000a097 -#define KEPLER_B 0x0000a197 -#define KEPLER_C 0x0000a297 - -#define MAXWELL_A 0x0000b097 -#define MAXWELL_B 0x0000b197 +#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a +#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a +#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a +#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a +#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a + +#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b +#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b +#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b +#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b +#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b + +#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c +#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c +#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c +#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c +#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c +#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c +#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c + +#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d +#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d +#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d +#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d +#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d +#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d +#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d +#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d +#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d +#define GM204_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d + +#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e +#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e +#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e +#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e +#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e +#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e + +#define FERMI_A /* cl9097.h */ 0x00009097 +#define FERMI_B /* cl9097.h */ 0x00009197 +#define FERMI_C /* cl9097.h */ 0x00009297 + +#define KEPLER_A /* cl9097.h */ 0x0000a097 +#define KEPLER_B /* cl9097.h */ 0x0000a197 +#define KEPLER_C /* cl9097.h */ 0x0000a297 + +#define MAXWELL_A /* cl9097.h */ 0x0000b097 +#define MAXWELL_B /* cl9097.h */ 0x0000b197 #define NV74_BSP 0x000074b0 @@ -133,540 +138,4 @@ #define MAXWELL_COMPUTE_B 0x0000b1c0 #define NV74_CIPHER 0x000074c1 - -/******************************************************************************* - * client - ******************************************************************************/ - -#define NV_CLIENT_DEVLIST 0x00 - -struct nv_client_devlist_v0 { - __u8 version; - __u8 count; - __u8 pad02[6]; - __u64 device[]; -}; - - -/******************************************************************************* - * device - ******************************************************************************/ - -struct nv_device_v0 { - __u8 version; - __u8 pad01[7]; - __u64 device; /* device identifier, ~0 for client default */ -}; - -#define NV_DEVICE_V0_INFO 0x00 -#define NV_DEVICE_V0_TIME 0x01 - -struct nv_device_info_v0 { - __u8 version; -#define NV_DEVICE_INFO_V0_IGP 0x00 -#define NV_DEVICE_INFO_V0_PCI 0x01 -#define NV_DEVICE_INFO_V0_AGP 0x02 -#define NV_DEVICE_INFO_V0_PCIE 0x03 -#define NV_DEVICE_INFO_V0_SOC 0x04 - __u8 platform; - __u16 chipset; /* from NV_PMC_BOOT_0 */ - __u8 revision; /* from NV_PMC_BOOT_0 */ -#define NV_DEVICE_INFO_V0_TNT 0x01 -#define NV_DEVICE_INFO_V0_CELSIUS 0x02 -#define NV_DEVICE_INFO_V0_KELVIN 0x03 -#define NV_DEVICE_INFO_V0_RANKINE 0x04 -#define NV_DEVICE_INFO_V0_CURIE 0x05 -#define NV_DEVICE_INFO_V0_TESLA 0x06 -#define NV_DEVICE_INFO_V0_FERMI 0x07 -#define NV_DEVICE_INFO_V0_KEPLER 0x08 -#define NV_DEVICE_INFO_V0_MAXWELL 0x09 - __u8 family; - __u8 pad06[2]; - __u64 ram_size; - __u64 ram_user; - char chip[16]; - char name[64]; -}; - -struct nv_device_time_v0 { - __u8 version; - __u8 pad01[7]; - __u64 time; -}; - - -/******************************************************************************* - * context dma - ******************************************************************************/ - -struct nv_dma_v0 { - __u8 version; -#define NV_DMA_V0_TARGET_VM 0x00 -#define NV_DMA_V0_TARGET_VRAM 0x01 -#define NV_DMA_V0_TARGET_PCI 0x02 -#define NV_DMA_V0_TARGET_PCI_US 0x03 -#define NV_DMA_V0_TARGET_AGP 0x04 - __u8 target; -#define NV_DMA_V0_ACCESS_VM 0x00 -#define NV_DMA_V0_ACCESS_RD 0x01 -#define NV_DMA_V0_ACCESS_WR 0x02 -#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) - __u8 access; - __u8 pad03[5]; - __u64 start; - __u64 limit; - /* ... chipset-specific class data */ -}; - -struct nv50_dma_v0 { - __u8 version; -#define NV50_DMA_V0_PRIV_VM 0x00 -#define NV50_DMA_V0_PRIV_US 0x01 -#define NV50_DMA_V0_PRIV__S 0x02 - __u8 priv; -#define NV50_DMA_V0_PART_VM 0x00 -#define NV50_DMA_V0_PART_256 0x01 -#define NV50_DMA_V0_PART_1KB 0x02 - __u8 part; -#define NV50_DMA_V0_COMP_NONE 0x00 -#define NV50_DMA_V0_COMP_1 0x01 -#define NV50_DMA_V0_COMP_2 0x02 -#define NV50_DMA_V0_COMP_VM 0x03 - __u8 comp; -#define NV50_DMA_V0_KIND_PITCH 0x00 -#define NV50_DMA_V0_KIND_VM 0x7f - __u8 kind; - __u8 pad05[3]; -}; - -struct gf100_dma_v0 { - __u8 version; -#define GF100_DMA_V0_PRIV_VM 0x00 -#define GF100_DMA_V0_PRIV_US 0x01 -#define GF100_DMA_V0_PRIV__S 0x02 - __u8 priv; -#define GF100_DMA_V0_KIND_PITCH 0x00 -#define GF100_DMA_V0_KIND_VM 0xff - __u8 kind; - __u8 pad03[5]; -}; - -struct gf119_dma_v0 { - __u8 version; -#define GF119_DMA_V0_PAGE_LP 0x00 -#define GF119_DMA_V0_PAGE_SP 0x01 - __u8 page; -#define GF119_DMA_V0_KIND_PITCH 0x00 -#define GF119_DMA_V0_KIND_VM 0xff - __u8 kind; - __u8 pad03[5]; -}; - - -/******************************************************************************* - * perfmon - ******************************************************************************/ - -#define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00 -#define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01 -#define NVIF_PERFMON_V0_QUERY_SOURCE 0x02 - -struct nvif_perfmon_query_domain_v0 { - __u8 version; - __u8 id; - __u8 counter_nr; - __u8 iter; - __u16 signal_nr; - __u8 pad05[2]; - char name[64]; -}; - -struct nvif_perfmon_query_signal_v0 { - __u8 version; - __u8 domain; - __u16 iter; - __u8 signal; - __u8 source_nr; - __u8 pad05[2]; - char name[64]; -}; - -struct nvif_perfmon_query_source_v0 { - __u8 version; - __u8 domain; - __u8 signal; - __u8 iter; - __u8 pad04[4]; - __u32 source; - __u32 mask; - char name[64]; -}; - - -/******************************************************************************* - * perfdom - ******************************************************************************/ - -struct nvif_perfdom_v0 { - __u8 version; - __u8 domain; - __u8 mode; - __u8 pad03[1]; - struct { - __u8 signal[4]; - __u64 source[4][8]; - __u16 logic_op; - } ctr[4]; -}; - -#define NVIF_PERFDOM_V0_INIT 0x00 -#define NVIF_PERFDOM_V0_SAMPLE 0x01 -#define NVIF_PERFDOM_V0_READ 0x02 - -struct nvif_perfdom_init { -}; - -struct nvif_perfdom_sample { -}; - -struct nvif_perfdom_read_v0 { - __u8 version; - __u8 pad01[7]; - __u32 ctr[4]; - __u32 clk; - __u8 pad04[4]; -}; - - -/******************************************************************************* - * device control - ******************************************************************************/ - -#define NVIF_CONTROL_PSTATE_INFO 0x00 -#define NVIF_CONTROL_PSTATE_ATTR 0x01 -#define NVIF_CONTROL_PSTATE_USER 0x02 - -struct nvif_control_pstate_info_v0 { - __u8 version; - __u8 count; /* out: number of power states */ -#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) -#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) - __s8 ustate_ac; /* out: target pstate index */ - __s8 ustate_dc; /* out: target pstate index */ - __s8 pwrsrc; /* out: current power source */ -#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) -#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) - __s8 pstate; /* out: current pstate index */ - __u8 pad06[2]; -}; - -struct nvif_control_pstate_attr_v0 { - __u8 version; -#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) - __s8 state; /* in: index of pstate to query - * out: pstate identifier - */ - __u8 index; /* in: index of attribute to query - * out: index of next attribute, or 0 if no more - */ - __u8 pad03[5]; - __u32 min; - __u32 max; - char name[32]; - char unit[16]; -}; - -struct nvif_control_pstate_user_v0 { - __u8 version; -#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) -#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) - __s8 ustate; /* in: pstate identifier */ - __s8 pwrsrc; /* in: target power source */ - __u8 pad03[5]; -}; - - -/******************************************************************************* - * DMA FIFO channels - ******************************************************************************/ - -struct nv03_channel_dma_v0 { - __u8 version; - __u8 chid; - __u8 pad02[2]; - __u32 offset; - __u64 pushbuf; -}; - -struct nv50_channel_dma_v0 { - __u8 version; - __u8 chid; - __u8 pad02[6]; - __u64 vm; - __u64 pushbuf; - __u64 offset; -}; - -#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 - -/******************************************************************************* - * GPFIFO channels - ******************************************************************************/ - -struct nv50_channel_gpfifo_v0 { - __u8 version; - __u8 chid; - __u8 pad02[2]; - __u32 ilength; - __u64 ioffset; - __u64 pushbuf; - __u64 vm; -}; - -struct fermi_channel_gpfifo_v0 { - __u8 version; - __u8 chid; - __u8 pad02[2]; - __u32 ilength; - __u64 ioffset; - __u64 vm; -}; - -struct kepler_channel_gpfifo_a_v0 { - __u8 version; -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 - __u8 engine; - __u16 chid; - __u32 ilength; - __u64 ioffset; - __u64 vm; -}; - -/******************************************************************************* - * legacy display - ******************************************************************************/ - -#define NV04_DISP_NTFY_VBLANK 0x00 -#define NV04_DISP_NTFY_CONN 0x01 - -struct nv04_disp_mthd_v0 { - __u8 version; -#define NV04_DISP_SCANOUTPOS 0x00 - __u8 method; - __u8 head; - __u8 pad03[5]; -}; - -struct nv04_disp_scanoutpos_v0 { - __u8 version; - __u8 pad01[7]; - __s64 time[2]; - __u16 vblanks; - __u16 vblanke; - __u16 vtotal; - __u16 vline; - __u16 hblanks; - __u16 hblanke; - __u16 htotal; - __u16 hline; -}; - -/******************************************************************************* - * display - ******************************************************************************/ - -#define NV50_DISP_MTHD 0x00 - -struct nv50_disp_mthd_v0 { - __u8 version; -#define NV50_DISP_SCANOUTPOS 0x00 - __u8 method; - __u8 head; - __u8 pad03[5]; -}; - -struct nv50_disp_mthd_v1 { - __u8 version; -#define NV50_DISP_MTHD_V1_DAC_PWR 0x10 -#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 -#define NV50_DISP_MTHD_V1_SOR_PWR 0x20 -#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 -#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 -#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 -#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 -#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 - __u8 method; - __u16 hasht; - __u16 hashm; - __u8 pad06[2]; -}; - -struct nv50_disp_dac_pwr_v0 { - __u8 version; - __u8 state; - __u8 data; - __u8 vsync; - __u8 hsync; - __u8 pad05[3]; -}; - -struct nv50_disp_dac_load_v0 { - __u8 version; - __u8 load; - __u8 pad02[2]; - __u32 data; -}; - -struct nv50_disp_sor_pwr_v0 { - __u8 version; - __u8 state; - __u8 pad02[6]; -}; - -struct nv50_disp_sor_hda_eld_v0 { - __u8 version; - __u8 pad01[7]; - __u8 data[]; -}; - -struct nv50_disp_sor_hdmi_pwr_v0 { - __u8 version; - __u8 state; - __u8 max_ac_packet; - __u8 rekey; - __u8 pad04[4]; -}; - -struct nv50_disp_sor_lvds_script_v0 { - __u8 version; - __u8 pad01[1]; - __u16 script; - __u8 pad04[4]; -}; - -struct nv50_disp_sor_dp_pwr_v0 { - __u8 version; - __u8 state; - __u8 pad02[6]; -}; - -struct nv50_disp_pior_pwr_v0 { - __u8 version; - __u8 state; - __u8 type; - __u8 pad03[5]; -}; - -/* core */ -struct nv50_disp_core_channel_dma_v0 { - __u8 version; - __u8 pad01[7]; - __u64 pushbuf; -}; - -#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 - -/* cursor immediate */ -struct nv50_disp_cursor_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; -}; - -#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 - -/* base */ -struct nv50_disp_base_channel_dma_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; - __u64 pushbuf; -}; - -#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 - -/* overlay */ -struct nv50_disp_overlay_channel_dma_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; - __u64 pushbuf; -}; - -#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 - -/* overlay immediate */ -struct nv50_disp_overlay_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; -}; - -#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 - -/******************************************************************************* - * software - ******************************************************************************/ - -#define NVSW_NTFY_UEVENT 0x00 - -#define NV04_NVSW_GET_REF 0x00 - -struct nv04_nvsw_get_ref_v0 { - __u8 version; - __u8 pad01[3]; - __u32 ref; -}; - -/******************************************************************************* - * fermi - ******************************************************************************/ - -#define FERMI_A_ZBC_COLOR 0x00 -#define FERMI_A_ZBC_DEPTH 0x01 - -struct fermi_a_zbc_color_v0 { - __u8 version; -#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 -#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 -#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 -#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 -#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c -#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 -#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 -#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 -#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 -#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c -#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 -#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 -#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 -#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c -#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 -#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 -#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 -#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c -#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 - __u8 format; - __u8 index; - __u8 pad03[5]; - __u32 ds[4]; - __u32 l2[4]; -}; - -struct fermi_a_zbc_depth_v0 { - __u8 version; -#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 - __u8 format; - __u8 index; - __u8 pad03[5]; - __u32 ds; - __u32 l2; -}; - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index 700a9b206726..e0ed2f4b2f43 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -2,7 +2,7 @@ #define __NVIF_DEVICE_H__ #include <nvif/object.h> -#include <nvif/class.h> +#include <nvif/cl0080.h> struct nvif_device { struct nvif_object object; @@ -63,6 +63,7 @@ u64 nvif_device_time(struct nvif_device *); #define nvxx_clk(a) nvxx_device(a)->clk #define nvxx_i2c(a) nvxx_device(a)->i2c #define nvxx_therm(a) nvxx_device(a)->therm +#define nvxx_volt(a) nvxx_device(a)->volt #include <core/device.h> #include <engine/fifo.h> diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0000.h b/drivers/gpu/drm/nouveau/include/nvif/if0000.h new file mode 100644 index 000000000000..85c44e8a1201 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0000.h @@ -0,0 +1,12 @@ +#ifndef __NVIF_IF0000_H__ +#define __NVIF_IF0000_H__ + +#define NV_CLIENT_DEVLIST 0x00 + +struct nv_client_devlist_v0 { + __u8 version; + __u8 count; + __u8 pad02[6]; + __u64 device[]; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0001.h b/drivers/gpu/drm/nouveau/include/nvif/if0001.h new file mode 100644 index 000000000000..bd5b64125eed --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0001.h @@ -0,0 +1,46 @@ +#ifndef __NVIF_IF0001_H__ +#define __NVIF_IF0001_H__ + +#define NVIF_CONTROL_PSTATE_INFO 0x00 +#define NVIF_CONTROL_PSTATE_ATTR 0x01 +#define NVIF_CONTROL_PSTATE_USER 0x02 + +struct nvif_control_pstate_info_v0 { + __u8 version; + __u8 count; /* out: number of power states */ +#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) +#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) + __s8 ustate_ac; /* out: target pstate index */ + __s8 ustate_dc; /* out: target pstate index */ + __s8 pwrsrc; /* out: current power source */ +#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) +#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) + __s8 pstate; /* out: current pstate index */ + __u8 pad06[2]; +}; + +struct nvif_control_pstate_attr_v0 { + __u8 version; +#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) + __s8 state; /* in: index of pstate to query + * out: pstate identifier + */ + __u8 index; /* in: index of attribute to query + * out: index of next attribute, or 0 if no more + */ + __u8 pad03[5]; + __u32 min; + __u32 max; + char name[32]; + char unit[16]; +}; + +struct nvif_control_pstate_user_v0 { + __u8 version; +#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) +#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) + __s8 ustate; /* in: pstate identifier */ + __s8 pwrsrc; /* in: target power source */ + __u8 pad03[5]; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0002.h b/drivers/gpu/drm/nouveau/include/nvif/if0002.h new file mode 100644 index 000000000000..c04c91d0b818 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0002.h @@ -0,0 +1,38 @@ +#ifndef __NVIF_IF0002_H__ +#define __NVIF_IF0002_H__ + +#define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00 +#define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01 +#define NVIF_PERFMON_V0_QUERY_SOURCE 0x02 + +struct nvif_perfmon_query_domain_v0 { + __u8 version; + __u8 id; + __u8 counter_nr; + __u8 iter; + __u16 signal_nr; + __u8 pad05[2]; + char name[64]; +}; + +struct nvif_perfmon_query_signal_v0 { + __u8 version; + __u8 domain; + __u16 iter; + __u8 signal; + __u8 source_nr; + __u8 pad05[2]; + char name[64]; +}; + +struct nvif_perfmon_query_source_v0 { + __u8 version; + __u8 domain; + __u8 signal; + __u8 iter; + __u8 pad04[4]; + __u32 source; + __u32 mask; + char name[64]; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0003.h b/drivers/gpu/drm/nouveau/include/nvif/if0003.h new file mode 100644 index 000000000000..0cd03efb80a1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0003.h @@ -0,0 +1,33 @@ +#ifndef __NVIF_IF0003_H__ +#define __NVIF_IF0003_H__ + +struct nvif_perfdom_v0 { + __u8 version; + __u8 domain; + __u8 mode; + __u8 pad03[1]; + struct { + __u8 signal[4]; + __u64 source[4][8]; + __u16 logic_op; + } ctr[4]; +}; + +#define NVIF_PERFDOM_V0_INIT 0x00 +#define NVIF_PERFDOM_V0_SAMPLE 0x01 +#define NVIF_PERFDOM_V0_READ 0x02 + +struct nvif_perfdom_init { +}; + +struct nvif_perfdom_sample { +}; + +struct nvif_perfdom_read_v0 { + __u8 version; + __u8 pad01[7]; + __u32 ctr[4]; + __u32 clk; + __u8 pad04[4]; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0004.h b/drivers/gpu/drm/nouveau/include/nvif/if0004.h new file mode 100644 index 000000000000..bd5cd428cfd7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0004.h @@ -0,0 +1,13 @@ +#ifndef __NVIF_IF0004_H__ +#define __NVIF_IF0004_H__ + +#define NV04_NVSW_NTFY_UEVENT 0x00 + +#define NV04_NVSW_GET_REF 0x00 + +struct nv04_nvsw_get_ref_v0 { + __u8 version; + __u8 pad01[3]; + __u32 ref; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0005.h b/drivers/gpu/drm/nouveau/include/nvif/if0005.h new file mode 100644 index 000000000000..abfd373bb68b --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0005.h @@ -0,0 +1,4 @@ +#ifndef __NVIF_IF0005_H__ +#define __NVIF_IF0005_H__ +#define NV10_NVSW_NTFY_UEVENT 0x00 +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/ioctl.h b/drivers/gpu/drm/nouveau/include/nvif/ioctl.h index b0ac0215ebf9..c5f5eb83a594 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/ioctl.h +++ b/drivers/gpu/drm/nouveau/include/nvif/ioctl.h @@ -55,14 +55,6 @@ struct nvif_ioctl_new_v0 { __u64 token; __u64 object; __u32 handle; -/* these class numbers are made up by us, and not nvidia-assigned */ -#define NVIF_IOCTL_NEW_V0_CONTROL -1 -#define NVIF_IOCTL_NEW_V0_PERFMON -2 -#define NVIF_IOCTL_NEW_V0_PERFDOM -3 -#define NVIF_IOCTL_NEW_V0_SW_NV04 -4 -#define NVIF_IOCTL_NEW_V0_SW_NV10 -5 -#define NVIF_IOCTL_NEW_V0_SW_NV50 -6 -#define NVIF_IOCTL_NEW_V0_SW_GF100 -7 __s32 oclass; __u8 data[]; /* class data (class.h) */ }; diff --git a/drivers/gpu/drm/nouveau/include/nvif/unpack.h b/drivers/gpu/drm/nouveau/include/nvif/unpack.h index 5933188b4a77..751bcf4930a7 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/unpack.h +++ b/drivers/gpu/drm/nouveau/include/nvif/unpack.h @@ -1,24 +1,28 @@ #ifndef __NVIF_UNPACK_H__ #define __NVIF_UNPACK_H__ -#define nvif_unvers(d) ({ \ - ret = (size == sizeof(d)) ? 0 : -ENOSYS; \ - (ret == 0); \ +#define nvif_unvers(r,d,s,m) ({ \ + void **_data = (d); __u32 *_size = (s); int _ret = (r); \ + if (_ret == -ENOSYS && *_size == sizeof(m)) { \ + *_data = NULL; \ + *_size = _ret = 0; \ + } \ + _ret; \ }) -#define nvif_unpack(d,vl,vh,m) ({ \ - if ((vl) == 0 || ret == -ENOSYS) { \ - int _size = sizeof(d); \ - if (_size <= size && (d).version >= (vl) && \ - (d).version <= (vh)) { \ - data = (u8 *)data + _size; \ - size = size - _size; \ - ret = ((m) || !size) ? 0 : -E2BIG; \ - } else { \ - ret = -ENOSYS; \ +#define nvif_unpack(r,d,s,m,vl,vh,x) ({ \ + void **_data = (d); __u32 *_size = (s); \ + int _ret = (r), _vl = (vl), _vh = (vh); \ + if (_ret == -ENOSYS && *_size >= sizeof(m) && \ + (m).version >= _vl && (m).version <= _vh) { \ + *_data = (__u8 *)*_data + sizeof(m); \ + *_size = *_size - sizeof(m); \ + if (_ret = 0, !(x)) { \ + _ret = *_size ? -E2BIG : 0; \ + *_data = NULL; \ + *_size = 0; \ } \ } \ - (ret == 0); \ + _ret; \ }) - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h index 7cc2becabc69..d3bd250103d5 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h @@ -13,6 +13,8 @@ struct nvbios_perfE { u32 vdec; u32 disp; u32 script; + u8 pcie_speed; + u8 pcie_width; }; u16 nvbios_perf_entry(struct nvkm_bios *, int idx, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h index 8708f0a4e188..6b33bc058924 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h @@ -2,6 +2,7 @@ #define __NVKM_CLK_H__ #include <core/subdev.h> #include <core/notify.h> +#include <subdev/pci.h> struct nvbios_pll; struct nvkm_pll_vals; @@ -38,7 +39,7 @@ enum nv_clk_src { nv_clk_src_hubk06, nv_clk_src_hubk07, nv_clk_src_copy, - nv_clk_src_daemon, + nv_clk_src_pmu, nv_clk_src_disp, nv_clk_src_vdec, @@ -59,6 +60,8 @@ struct nvkm_pstate { struct nvkm_cstate base; u8 pstate; u8 fanspeed; + enum nvkm_pcie_speed pcie_speed; + u8 pcie_width; }; struct nvkm_domain { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h index c4dcd2680fe1..ea23e24a246c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h @@ -6,4 +6,5 @@ int gf100_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); int gf117_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); int gk104_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); int gk20a_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); +int gm204_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h index 3d4dbbf9aab3..0ffa2ec106d6 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h @@ -37,4 +37,5 @@ int gf100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gk104_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gk20a_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); +int gm204_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h index fee0a97c44c5..ddb913889d7e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h @@ -2,6 +2,12 @@ #define __NVKM_PCI_H__ #include <core/subdev.h> +enum nvkm_pcie_speed { + NVKM_PCIE_SPEED_2_5, + NVKM_PCIE_SPEED_5_0, + NVKM_PCIE_SPEED_8_0, +}; + struct nvkm_pci { const struct nvkm_pci_func *func; struct nvkm_subdev subdev; @@ -18,6 +24,11 @@ struct nvkm_pci { bool acquired; } agp; + struct { + enum nvkm_pcie_speed speed; + u8 width; + } pcie; + bool msi; }; @@ -34,4 +45,9 @@ int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int g84_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int g94_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **); +int gf106_pci_new(struct nvkm_device *, int, struct nvkm_pci **); +int gk104_pci_new(struct nvkm_device *, int, struct nvkm_pci **); + +/* pcie functions */ +int nvkm_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8 width); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 7f50cf5f929e..50f52ffe5b0c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -25,6 +25,8 @@ #include <nvif/driver.h> #include <nvif/ioctl.h> #include <nvif/class.h> +#include <nvif/cl0002.h> +#include <nvif/cla06f.h> #include <nvif/unpack.h> #include "nouveau_drm.h" @@ -87,18 +89,18 @@ nouveau_abi16_swclass(struct nouveau_drm *drm) { switch (drm->device.info.family) { case NV_DEVICE_INFO_V0_TNT: - return NVIF_IOCTL_NEW_V0_SW_NV04; + return NVIF_CLASS_SW_NV04; case NV_DEVICE_INFO_V0_CELSIUS: case NV_DEVICE_INFO_V0_KELVIN: case NV_DEVICE_INFO_V0_RANKINE: case NV_DEVICE_INFO_V0_CURIE: - return NVIF_IOCTL_NEW_V0_SW_NV10; + return NVIF_CLASS_SW_NV10; case NV_DEVICE_INFO_V0_TESLA: - return NVIF_IOCTL_NEW_V0_SW_NV50; + return NVIF_CLASS_SW_NV50; case NV_DEVICE_INFO_V0_FERMI: case NV_DEVICE_INFO_V0_KEPLER: case NV_DEVICE_INFO_V0_MAXWELL: - return NVIF_IOCTL_NEW_V0_SW_GF100; + return NVIF_CLASS_SW_GF100; } return 0x0000; @@ -355,9 +357,9 @@ nouveau_abi16_usif(struct drm_file *file_priv, void *data, u32 size) } *args = data; struct nouveau_abi16_chan *chan; struct nouveau_abi16 *abi16; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { switch (args->v0.type) { case NVIF_IOCTL_V0_NEW: case NVIF_IOCTL_V0_MTHD: @@ -433,10 +435,10 @@ nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS) /* nvsw: compatibility with older 0x*6e class identifier */ for (i = 0; !oclass && i < ret; i++) { switch (sclass[i].oclass) { - case NVIF_IOCTL_NEW_V0_SW_NV04: - case NVIF_IOCTL_NEW_V0_SW_NV10: - case NVIF_IOCTL_NEW_V0_SW_NV50: - case NVIF_IOCTL_NEW_V0_SW_GF100: + case NVIF_CLASS_SW_NV04: + case NVIF_CLASS_SW_NV10: + case NVIF_CLASS_SW_NV50: + case NVIF_CLASS_SW_GF100: oclass = sclass[i].oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 1860f389f21f..3f804a8c590c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -24,6 +24,11 @@ #include <nvif/os.h> #include <nvif/class.h> +#include <nvif/cl0002.h> +#include <nvif/cl006b.h> +#include <nvif/cl506f.h> +#include <nvif/cl906f.h> +#include <nvif/cla06f.h> #include <nvif/ioctl.h> /*XXX*/ @@ -378,7 +383,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) /* allocate software object class (used for fences on <= nv05) */ if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { ret = nvif_object_init(&chan->user, 0x006e, - NVIF_IOCTL_NEW_V0_SW_NV04, + NVIF_CLASS_SW_NV04, NULL, 0, &chan->nvsw); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 5dd1d0111cac..fcebfae5d426 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -42,6 +42,8 @@ #include "nouveau_encoder.h" #include "nouveau_crtc.h" +#include <nvif/class.h> +#include <nvif/cl0046.h> #include <nvif/event.h> MODULE_PARM_DESC(tv_disable, "Disable TV-out detection"); @@ -56,6 +58,10 @@ MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (default: enabled)"); int nouveau_duallink = 1; module_param_named(duallink, nouveau_duallink, int, 0400); +MODULE_PARM_DESC(hdmimhz, "Force a maximum HDMI pixel clock (in MHz)"); +int nouveau_hdmimhz = 0; +module_param_named(hdmimhz, nouveau_hdmimhz, int, 0400); + struct nouveau_encoder * find_encoder(struct drm_connector *connector, int type) { @@ -809,12 +815,23 @@ nouveau_connector_get_modes(struct drm_connector *connector) } static unsigned -get_tmds_link_bandwidth(struct drm_connector *connector) +get_tmds_link_bandwidth(struct drm_connector *connector, bool hdmi) { struct nouveau_connector *nv_connector = nouveau_connector(connector); struct nouveau_drm *drm = nouveau_drm(connector->dev); struct dcb_output *dcb = nv_connector->detected_encoder->dcb; + if (hdmi) { + if (nouveau_hdmimhz > 0) + return nouveau_hdmimhz * 1000; + /* Note: these limits are conservative, some Fermi's + * can do 297 MHz. Unclear how this can be determined. + */ + if (drm->device.info.family >= NV_DEVICE_INFO_V0_KEPLER) + return 297000; + if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI) + return 225000; + } if (dcb->location != DCB_LOC_ON_CHIP || drm->device.info.chipset >= 0x46) return 165000; @@ -835,6 +852,7 @@ nouveau_connector_mode_valid(struct drm_connector *connector, struct drm_encoder *encoder = to_drm_encoder(nv_encoder); unsigned min_clock = 25000, max_clock = min_clock; unsigned clock = mode->clock; + bool hdmi; switch (nv_encoder->dcb->type) { case DCB_OUTPUT_LVDS: @@ -847,8 +865,10 @@ nouveau_connector_mode_valid(struct drm_connector *connector, max_clock = 400000; break; case DCB_OUTPUT_TMDS: - max_clock = get_tmds_link_bandwidth(connector); - if (nouveau_duallink && nv_encoder->dcb->duallink_possible) + hdmi = drm_detect_hdmi_monitor(nv_connector->edid); + max_clock = get_tmds_link_bandwidth(connector, hdmi); + if (!hdmi && nouveau_duallink && + nv_encoder->dcb->duallink_possible) max_clock *= 2; break; case DCB_OUTPUT_ANALOG: @@ -963,10 +983,13 @@ nouveau_connector_hotplug(struct nvif_notify *notify) NV_DEBUG(drm, "%splugged %s\n", plugged ? "" : "un", name); + mutex_lock(&drm->dev->mode_config.mutex); if (plugged) drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); else drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); + mutex_unlock(&drm->dev->mode_config.mutex); + drm_helper_hpd_irq_event(connector->dev); } diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c index 5392e07edfc6..3d0dc199b253 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c @@ -28,6 +28,9 @@ * Ben Skeggs <bskeggs@redhat.com> */ +#include <linux/debugfs.h> +#include <nvif/class.h> +#include <nvif/if0001.h> #include "nouveau_debugfs.h" #include "nouveau_drm.h" @@ -43,22 +46,233 @@ nouveau_debugfs_vbios_image(struct seq_file *m, void *data) return 0; } +static int +nouveau_debugfs_pstate_get(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct nouveau_debugfs *debugfs = nouveau_debugfs(node->minor->dev); + struct nvif_object *ctrl = &debugfs->ctrl; + struct nvif_control_pstate_info_v0 info = {}; + int ret, i; + + if (!debugfs) + return -ENODEV; + + ret = nvif_mthd(ctrl, NVIF_CONTROL_PSTATE_INFO, &info, sizeof(info)); + if (ret) + return ret; + + for (i = 0; i < info.count + 1; i++) { + const s32 state = i < info.count ? i : + NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT; + struct nvif_control_pstate_attr_v0 attr = { + .state = state, + .index = 0, + }; + + ret = nvif_mthd(ctrl, NVIF_CONTROL_PSTATE_ATTR, + &attr, sizeof(attr)); + if (ret) + return ret; + + if (i < info.count) + seq_printf(m, "%02x:", attr.state); + else + seq_printf(m, "%s:", info.pwrsrc == 0 ? "DC" : + info.pwrsrc == 1 ? "AC" : "--"); + + attr.index = 0; + do { + attr.state = state; + ret = nvif_mthd(ctrl, NVIF_CONTROL_PSTATE_ATTR, + &attr, sizeof(attr)); + if (ret) + return ret; + + seq_printf(m, " %s %d", attr.name, attr.min); + if (attr.min != attr.max) + seq_printf(m, "-%d", attr.max); + seq_printf(m, " %s", attr.unit); + } while (attr.index); + + if (state >= 0) { + if (info.ustate_ac == state) + seq_printf(m, " AC"); + if (info.ustate_dc == state) + seq_printf(m, " DC"); + if (info.pstate == state) + seq_printf(m, " *"); + } else { + if (info.ustate_ac < -1) + seq_printf(m, " AC"); + if (info.ustate_dc < -1) + seq_printf(m, " DC"); + } + + seq_printf(m, "\n"); + } + + return 0; +} + +static ssize_t +nouveau_debugfs_pstate_set(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct nouveau_debugfs *debugfs = nouveau_debugfs(node->minor->dev); + struct nvif_object *ctrl = &debugfs->ctrl; + struct nvif_control_pstate_user_v0 args = { .pwrsrc = -EINVAL }; + char buf[32] = {}, *tmp, *cur = buf; + long value, ret; + + if (!debugfs) + return -ENODEV; + + if (len >= sizeof(buf)) + return -EINVAL; + + if (copy_from_user(buf, ubuf, len)) + return -EFAULT; + + if ((tmp = strchr(buf, '\n'))) + *tmp = '\0'; + + if (!strncasecmp(cur, "dc:", 3)) { + args.pwrsrc = 0; + cur += 3; + } else + if (!strncasecmp(cur, "ac:", 3)) { + args.pwrsrc = 1; + cur += 3; + } + + if (!strcasecmp(cur, "none")) + args.ustate = NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN; + else + if (!strcasecmp(cur, "auto")) + args.ustate = NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON; + else { + ret = kstrtol(cur, 16, &value); + if (ret) + return ret; + args.ustate = value; + } + + ret = nvif_mthd(ctrl, NVIF_CONTROL_PSTATE_USER, &args, sizeof(args)); + if (ret < 0) + return ret; + + return len; +} + +static int +nouveau_debugfs_pstate_open(struct inode *inode, struct file *file) +{ + return single_open(file, nouveau_debugfs_pstate_get, inode->i_private); +} + +static const struct file_operations nouveau_pstate_fops = { + .owner = THIS_MODULE, + .open = nouveau_debugfs_pstate_open, + .read = seq_read, + .write = nouveau_debugfs_pstate_set, +}; + static struct drm_info_list nouveau_debugfs_list[] = { { "vbios.rom", nouveau_debugfs_vbios_image, 0, NULL }, }; #define NOUVEAU_DEBUGFS_ENTRIES ARRAY_SIZE(nouveau_debugfs_list) -int -nouveau_debugfs_init(struct drm_minor *minor) +static const struct nouveau_debugfs_files { + const char *name; + const struct file_operations *fops; +} nouveau_debugfs_files[] = { + {"pstate", &nouveau_pstate_fops}, +}; + +static int +nouveau_debugfs_create_file(struct drm_minor *minor, + const struct nouveau_debugfs_files *ndf) { - drm_debugfs_create_files(nouveau_debugfs_list, NOUVEAU_DEBUGFS_ENTRIES, - minor->debugfs_root, minor); + struct drm_info_node *node; + + node = kmalloc(sizeof(*node), GFP_KERNEL); + if (node == NULL) + return -ENOMEM; + + node->minor = minor; + node->info_ent = (const void *)ndf->fops; + node->dent = debugfs_create_file(ndf->name, S_IRUGO | S_IWUSR, + minor->debugfs_root, node, ndf->fops); + if (!node->dent) { + kfree(node); + return -ENOMEM; + } + + mutex_lock(&minor->debugfs_lock); + list_add(&node->list, &minor->debugfs_list); + mutex_unlock(&minor->debugfs_lock); return 0; } +int +nouveau_drm_debugfs_init(struct drm_minor *minor) +{ + int i, ret; + + for (i = 0; i < ARRAY_SIZE(nouveau_debugfs_files); i++) { + ret = nouveau_debugfs_create_file(minor, + &nouveau_debugfs_files[i]); + + if (ret) + return ret; + } + + return drm_debugfs_create_files(nouveau_debugfs_list, + NOUVEAU_DEBUGFS_ENTRIES, + minor->debugfs_root, minor); +} + void -nouveau_debugfs_takedown(struct drm_minor *minor) +nouveau_drm_debugfs_cleanup(struct drm_minor *minor) { + int i; + drm_debugfs_remove_files(nouveau_debugfs_list, NOUVEAU_DEBUGFS_ENTRIES, minor); + + for (i = 0; i < ARRAY_SIZE(nouveau_debugfs_files); i++) { + drm_debugfs_remove_files((struct drm_info_list *) + nouveau_debugfs_files[i].fops, + 1, minor); + } +} + +int +nouveau_debugfs_init(struct nouveau_drm *drm) +{ + int ret; + + drm->debugfs = kzalloc(sizeof(*drm->debugfs), GFP_KERNEL); + if (!drm->debugfs) + return -ENOMEM; + + ret = nvif_object_init(&drm->device.object, 0, NVIF_CLASS_CONTROL, + NULL, 0, &drm->debugfs->ctrl); + if (ret) + return ret; + + return 0; +} + +void +nouveau_debugfs_fini(struct nouveau_drm *drm) +{ + if (drm->debugfs && drm->debugfs->ctrl.priv) + nvif_object_fini(&drm->debugfs->ctrl); + + kfree(drm->debugfs); + drm->debugfs = NULL; } diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.h b/drivers/gpu/drm/nouveau/nouveau_debugfs.h index a62af6fb5f99..52c7161297d7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.h +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.h @@ -4,16 +4,43 @@ #include <drm/drmP.h> #if defined(CONFIG_DEBUG_FS) -extern int nouveau_debugfs_init(struct drm_minor *); -extern void nouveau_debugfs_takedown(struct drm_minor *); + +#include "nouveau_drm.h" + +struct nouveau_debugfs { + struct nvif_object ctrl; +}; + +static inline struct nouveau_debugfs * +nouveau_debugfs(struct drm_device *dev) +{ + return nouveau_drm(dev)->debugfs; +} + +extern int nouveau_drm_debugfs_init(struct drm_minor *); +extern void nouveau_drm_debugfs_cleanup(struct drm_minor *); +extern int nouveau_debugfs_init(struct nouveau_drm *); +extern void nouveau_debugfs_fini(struct nouveau_drm *); #else static inline int -nouveau_debugfs_init(struct drm_minor *minor) +nouveau_drm_debugfs_init(struct drm_minor *minor) { return 0; } -static inline void nouveau_debugfs_takedown(struct drm_minor *minor) +static inline void +nouveau_drm_debugfs_cleanup(struct drm_minor *minor) +{ +} + +static inline int +nouveau_debugfs_init(struct nouveau_drm *) +{ + return 0; +} + +static inline void +nouveau_debugfs_fini(struct nouveau_drm *) { } diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 18676b8c1721..24be27d3cd18 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -39,6 +39,7 @@ #include "nouveau_fence.h" +#include <nvif/cl0046.h> #include <nvif/event.h> static int diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index b3a563c44bcd..2f2f252e3fb6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -37,12 +37,16 @@ #include <core/pci.h> #include <core/tegra.h> +#include <nvif/class.h> +#include <nvif/cl0002.h> +#include <nvif/cla06f.h> +#include <nvif/if0004.h> + #include "nouveau_drm.h" #include "nouveau_dma.h" #include "nouveau_ttm.h" #include "nouveau_gem.h" #include "nouveau_vga.h" -#include "nouveau_sysfs.h" #include "nouveau_hwmon.h" #include "nouveau_acpi.h" #include "nouveau_bios.h" @@ -256,8 +260,8 @@ nouveau_accel_init(struct nouveau_drm *drm) } ret = nvif_notify_init(&drm->nvsw, nouveau_flip_complete, - false, NVSW_NTFY_UEVENT, NULL, 0, 0, - &drm->flip); + false, NV04_NVSW_NTFY_UEVENT, + NULL, 0, 0, &drm->flip); if (ret == 0) ret = nvif_notify_get(&drm->flip); if (ret) { @@ -448,7 +452,7 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags) goto fail_dispinit; } - nouveau_sysfs_init(dev); + nouveau_debugfs_init(drm); nouveau_hwmon_init(dev); nouveau_accel_init(drm); nouveau_fbcon_init(dev); @@ -486,7 +490,7 @@ nouveau_drm_unload(struct drm_device *dev) nouveau_fbcon_fini(dev); nouveau_accel_fini(drm); nouveau_hwmon_fini(dev); - nouveau_sysfs_fini(dev); + nouveau_debugfs_fini(drm); if (dev->mode_config.num_crtc) nouveau_display_fini(dev); @@ -928,8 +932,8 @@ driver_stub = { .lastclose = nouveau_vga_lastclose, #if defined(CONFIG_DEBUG_FS) - .debugfs_init = nouveau_debugfs_init, - .debugfs_cleanup = nouveau_debugfs_takedown, + .debugfs_init = nouveau_drm_debugfs_init, + .debugfs_cleanup = nouveau_drm_debugfs_cleanup, #endif .get_vblank_counter = drm_vblank_no_hw_counter, @@ -1003,7 +1007,6 @@ static void nouveau_display_options(void) DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); - DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate); } static const struct dev_pm_ops nouveau_pm_ops = { diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h index a02813e994ec..5c363ed1c842 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.h +++ b/drivers/gpu/drm/nouveau/nouveau_drm.h @@ -164,7 +164,7 @@ struct nouveau_drm { /* power management */ struct nouveau_hwmon *hwmon; - struct nouveau_sysfs *sysfs; + struct nouveau_debugfs *debugfs; /* display power reference */ bool have_disp_power_ref; diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index 574c36b492ee..9a8c5b727f59 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -30,6 +30,7 @@ #include <linux/hrtimer.h> #include <trace/events/fence.h> +#include <nvif/cl826e.h> #include <nvif/notify.h> #include <nvif/event.h> diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c index 491c7149d197..8e13467d0ddb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c +++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c @@ -34,6 +34,8 @@ #include "nouveau_drm.h" #include "nouveau_hwmon.h" +#include <nvkm/subdev/volt.h> + #if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) static ssize_t nouveau_hwmon_show_temp(struct device *d, struct device_attribute *a, char *buf) @@ -512,6 +514,35 @@ static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO | S_IWUSR, nouveau_hwmon_get_pwm1_max, nouveau_hwmon_set_pwm1_max, 0); +static ssize_t +nouveau_hwmon_get_in0_input(struct device *d, + struct device_attribute *a, char *buf) +{ + struct drm_device *dev = dev_get_drvdata(d); + struct nouveau_drm *drm = nouveau_drm(dev); + struct nvkm_volt *volt = nvxx_volt(&drm->device); + int ret; + + ret = nvkm_volt_get(volt); + if (ret < 0) + return ret; + + return sprintf(buf, "%i\n", ret / 1000); +} + +static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, + nouveau_hwmon_get_in0_input, NULL, 0); + +static ssize_t +nouveau_hwmon_get_in0_label(struct device *d, + struct device_attribute *a, char *buf) +{ + return sprintf(buf, "GPU core\n"); +} + +static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, + nouveau_hwmon_get_in0_label, NULL, 0); + static struct attribute *hwmon_default_attributes[] = { &sensor_dev_attr_name.dev_attr.attr, &sensor_dev_attr_update_rate.dev_attr.attr, @@ -542,6 +573,12 @@ static struct attribute *hwmon_pwm_fan_attributes[] = { NULL }; +static struct attribute *hwmon_in0_attributes[] = { + &sensor_dev_attr_in0_input.dev_attr.attr, + &sensor_dev_attr_in0_label.dev_attr.attr, + NULL +}; + static const struct attribute_group hwmon_default_attrgroup = { .attrs = hwmon_default_attributes, }; @@ -554,6 +591,9 @@ static const struct attribute_group hwmon_fan_rpm_attrgroup = { static const struct attribute_group hwmon_pwm_fan_attrgroup = { .attrs = hwmon_pwm_fan_attributes, }; +static const struct attribute_group hwmon_in0_attrgroup = { + .attrs = hwmon_in0_attributes, +}; #endif int @@ -562,6 +602,7 @@ nouveau_hwmon_init(struct drm_device *dev) #if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) struct nouveau_drm *drm = nouveau_drm(dev); struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_volt *volt = nvxx_volt(&drm->device); struct nouveau_hwmon *hwmon; struct device *hwmon_dev; int ret = 0; @@ -613,6 +654,14 @@ nouveau_hwmon_init(struct drm_device *dev) goto error; } + if (volt && nvkm_volt_get(volt) >= 0) { + ret = sysfs_create_group(&hwmon_dev->kobj, + &hwmon_in0_attrgroup); + + if (ret) + goto error; + } + hwmon->hwmon = hwmon_dev; return 0; @@ -638,6 +687,7 @@ nouveau_hwmon_fini(struct drm_device *dev) sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_temp_attrgroup); sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_pwm_fan_attrgroup); sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_fan_rpm_attrgroup); + sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_in0_attrgroup); hwmon_device_unregister(hwmon->hwmon); } diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c index 60e32c4e4e49..8a70cec59bcd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_platform.c +++ b/drivers/gpu/drm/nouveau/nouveau_platform.c @@ -78,3 +78,14 @@ struct platform_driver nouveau_platform_driver = { .probe = nouveau_platform_probe, .remove = nouveau_platform_remove, }; + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) || IS_ENABLED(CONFIG_ARCH_TEGRA_132_SOC) +MODULE_FIRMWARE("nvidia/gk20a/fecs_data.bin"); +MODULE_FIRMWARE("nvidia/gk20a/fecs_inst.bin"); +MODULE_FIRMWARE("nvidia/gk20a/gpccs_data.bin"); +MODULE_FIRMWARE("nvidia/gk20a/gpccs_inst.bin"); +MODULE_FIRMWARE("nvidia/gk20a/sw_bundle_init.bin"); +MODULE_FIRMWARE("nvidia/gk20a/sw_ctx.bin"); +MODULE_FIRMWARE("nvidia/gk20a/sw_method_init.bin"); +MODULE_FIRMWARE("nvidia/gk20a/sw_nonctx.bin"); +#endif diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.c b/drivers/gpu/drm/nouveau/nouveau_sysfs.c deleted file mode 100644 index 5dac3546c1b8..000000000000 --- a/drivers/gpu/drm/nouveau/nouveau_sysfs.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs <bskeggs@redhat.com> - */ - -#include <nvif/os.h> -#include <nvif/class.h> -#include <nvif/ioctl.h> - -#include "nouveau_sysfs.h" - -MODULE_PARM_DESC(pstate, "enable sysfs pstate file, which will be moved in the future"); -int nouveau_pstate; -module_param_named(pstate, nouveau_pstate, int, 0400); - -static inline struct drm_device * -drm_device(struct device *d) -{ - return dev_get_drvdata(d); -} - -#define snappendf(p,r,f,a...) do { \ - snprintf(p, r, f, ##a); \ - r -= strlen(p); \ - p += strlen(p); \ -} while(0) - -static ssize_t -nouveau_sysfs_pstate_get(struct device *d, struct device_attribute *a, char *b) -{ - struct nouveau_sysfs *sysfs = nouveau_sysfs(drm_device(d)); - struct nvif_control_pstate_info_v0 info = {}; - size_t cnt = PAGE_SIZE; - char *buf = b; - int ret, i; - - ret = nvif_mthd(&sysfs->ctrl, NVIF_CONTROL_PSTATE_INFO, - &info, sizeof(info)); - if (ret) - return ret; - - for (i = 0; i < info.count + 1; i++) { - const s32 state = i < info.count ? i : - NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT; - struct nvif_control_pstate_attr_v0 attr = { - .state = state, - .index = 0, - }; - - ret = nvif_mthd(&sysfs->ctrl, NVIF_CONTROL_PSTATE_ATTR, - &attr, sizeof(attr)); - if (ret) - return ret; - - if (i < info.count) - snappendf(buf, cnt, "%02x:", attr.state); - else - snappendf(buf, cnt, "%s:", info.pwrsrc == 0 ? "DC" : - info.pwrsrc == 1 ? "AC" : - "--"); - - attr.index = 0; - do { - attr.state = state; - ret = nvif_mthd(&sysfs->ctrl, - NVIF_CONTROL_PSTATE_ATTR, - &attr, sizeof(attr)); - if (ret) - return ret; - - snappendf(buf, cnt, " %s %d", attr.name, attr.min); - if (attr.min != attr.max) - snappendf(buf, cnt, "-%d", attr.max); - snappendf(buf, cnt, " %s", attr.unit); - } while (attr.index); - - if (state >= 0) { - if (info.ustate_ac == state) - snappendf(buf, cnt, " AC"); - if (info.ustate_dc == state) - snappendf(buf, cnt, " DC"); - if (info.pstate == state) - snappendf(buf, cnt, " *"); - } else { - if (info.ustate_ac < -1) - snappendf(buf, cnt, " AC"); - if (info.ustate_dc < -1) - snappendf(buf, cnt, " DC"); - } - - snappendf(buf, cnt, "\n"); - } - - return strlen(b); -} - -static ssize_t -nouveau_sysfs_pstate_set(struct device *d, struct device_attribute *a, - const char *buf, size_t count) -{ - struct nouveau_sysfs *sysfs = nouveau_sysfs(drm_device(d)); - struct nvif_control_pstate_user_v0 args = { .pwrsrc = -EINVAL }; - long value, ret; - char *tmp; - - if ((tmp = strchr(buf, '\n'))) - *tmp = '\0'; - - if (!strncasecmp(buf, "dc:", 3)) { - args.pwrsrc = 0; - buf += 3; - } else - if (!strncasecmp(buf, "ac:", 3)) { - args.pwrsrc = 1; - buf += 3; - } - - if (!strcasecmp(buf, "none")) - args.ustate = NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN; - else - if (!strcasecmp(buf, "auto")) - args.ustate = NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON; - else { - ret = kstrtol(buf, 16, &value); - if (ret) - return ret; - args.ustate = value; - } - - ret = nvif_mthd(&sysfs->ctrl, NVIF_CONTROL_PSTATE_USER, - &args, sizeof(args)); - if (ret < 0) - return ret; - - return count; -} - -static DEVICE_ATTR(pstate, S_IRUGO | S_IWUSR, - nouveau_sysfs_pstate_get, nouveau_sysfs_pstate_set); - -void -nouveau_sysfs_fini(struct drm_device *dev) -{ - struct nouveau_sysfs *sysfs = nouveau_sysfs(dev); - struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_device *device = &drm->device; - - if (sysfs && sysfs->ctrl.priv) { - device_remove_file(nvxx_device(device)->dev, &dev_attr_pstate); - nvif_object_fini(&sysfs->ctrl); - } - - drm->sysfs = NULL; - kfree(sysfs); -} - -int -nouveau_sysfs_init(struct drm_device *dev) -{ - struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_device *device = &drm->device; - struct nouveau_sysfs *sysfs; - int ret; - - if (!nouveau_pstate) - return 0; - - sysfs = drm->sysfs = kzalloc(sizeof(*sysfs), GFP_KERNEL); - if (!sysfs) - return -ENOMEM; - - ret = nvif_object_init(&device->object, 0, NVIF_IOCTL_NEW_V0_CONTROL, - NULL, 0, &sysfs->ctrl); - if (ret == 0) - device_create_file(nvxx_device(device)->dev, &dev_attr_pstate); - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.h b/drivers/gpu/drm/nouveau/nouveau_sysfs.h deleted file mode 100644 index 4e5ea9241b28..000000000000 --- a/drivers/gpu/drm/nouveau/nouveau_sysfs.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __NOUVEAU_SYSFS_H__ -#define __NOUVEAU_SYSFS_H__ - -#include "nouveau_drm.h" - -struct nouveau_sysfs { - struct nvif_object ctrl; -}; - -static inline struct nouveau_sysfs * -nouveau_sysfs(struct drm_device *dev) -{ - return nouveau_drm(dev)->sysfs; -} - -int nouveau_sysfs_init(struct drm_device *); -void nouveau_sysfs_fini(struct drm_device *); - -extern int nouveau_pstate; - -#endif diff --git a/drivers/gpu/drm/nouveau/nouveau_usif.c b/drivers/gpu/drm/nouveau/nouveau_usif.c index 6ae1b3494bcd..e9f52ef0be83 100644 --- a/drivers/gpu/drm/nouveau/nouveau_usif.c +++ b/drivers/gpu/drm/nouveau/nouveau_usif.c @@ -130,20 +130,21 @@ usif_notify_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) struct nvif_notify_req_v0 v0; } *req; struct usif_notify *ntfy; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { if (usif_notify_find(f, args->v0.index)) return -EEXIST; } else return ret; req = data; + ret = -ENOSYS; if (!(ntfy = kmalloc(sizeof(*ntfy), GFP_KERNEL))) return -ENOMEM; atomic_set(&ntfy->enabled, 0); - if (nvif_unpack(req->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, true))) { ntfy->reply = sizeof(struct nvif_notify_rep_v0) + req->v0.reply; ntfy->route = req->v0.route; ntfy->token = req->v0.token; @@ -171,9 +172,9 @@ usif_notify_del(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) struct nvif_ioctl_ntfy_del_v0 v0; } *args = data; struct usif_notify *ntfy; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { if (!(ntfy = usif_notify_find(f, args->v0.index))) return -ENOENT; } else @@ -194,9 +195,9 @@ usif_notify_get(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) struct nvif_ioctl_ntfy_del_v0 v0; } *args = data; struct usif_notify *ntfy; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { if (!(ntfy = usif_notify_find(f, args->v0.index))) return -ENOENT; } else @@ -233,9 +234,9 @@ usif_notify_put(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) struct nvif_ioctl_ntfy_put_v0 v0; } *args = data; struct usif_notify *ntfy; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { if (!(ntfy = usif_notify_find(f, args->v0.index))) return -ENOENT; } else @@ -270,13 +271,13 @@ usif_object_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) struct nvif_ioctl_new_v0 v0; } *args = data; struct usif_object *object; - int ret; + int ret = -ENOSYS; if (!(object = kmalloc(sizeof(*object), GFP_KERNEL))) return -ENOMEM; list_add(&object->head, &cli->objects); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { object->route = args->v0.route; object->token = args->v0.token; args->v0.route = NVDRM_OBJECT_USIF; @@ -310,7 +311,7 @@ usif_ioctl(struct drm_file *filp, void __user *user, u32 argc) if (ret = -EFAULT, copy_from_user(argv, user, size)) goto done; - if (nvif_unpack(argv->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(-ENOSYS, &data, &size, argv->v0, 0, 0, true))) { /* block access to objects not created via this interface */ owner = argv->v0.owner; if (argv->v0.object == 0ULL) diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c index f3d705d67738..3022d24ed88b 100644 --- a/drivers/gpu/drm/nouveau/nv04_fence.c +++ b/drivers/gpu/drm/nouveau/nv04_fence.c @@ -26,6 +26,8 @@ #include "nouveau_dma.h" #include "nouveau_fence.h" +#include <nvif/if0004.h> + struct nv04_fence_chan { struct nouveau_fence_chan base; }; diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c index 80b6eb8b3d02..6a141c9bf5b7 100644 --- a/drivers/gpu/drm/nouveau/nv17_fence.c +++ b/drivers/gpu/drm/nouveau/nv17_fence.c @@ -24,6 +24,7 @@ #include <nvif/os.h> #include <nvif/class.h> +#include <nvif/cl0002.h> #include "nouveau_drm.h" #include "nouveau_dma.h" diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 44e1952582aa..ea3921652449 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -31,6 +31,13 @@ #include <drm/drm_fb_helper.h> #include <nvif/class.h> +#include <nvif/cl0002.h> +#include <nvif/cl5070.h> +#include <nvif/cl507a.h> +#include <nvif/cl507b.h> +#include <nvif/cl507c.h> +#include <nvif/cl507d.h> +#include <nvif/cl507e.h> #include "nouveau_drm.h" #include "nouveau_dma.h" @@ -774,7 +781,6 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) */ if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || (nv_connector->underscan == UNDERSCAN_AUTO && - nv_connector->edid && drm_detect_hdmi_monitor(nv_connector->edid)))) { u32 bX = nv_connector->underscan_hborder; u32 bY = nv_connector->underscan_vborder; @@ -1962,10 +1968,17 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, switch (nv_encoder->dcb->type) { case DCB_OUTPUT_TMDS: if (nv_encoder->dcb->sorconf.link & 1) { - if (mode->clock < 165000) - proto = 0x1; - else - proto = 0x5; + proto = 0x1; + /* Only enable dual-link if: + * - Need to (i.e. rate > 165MHz) + * - DCB says we can + * - Not an HDMI monitor, since there's no dual-link + * on HDMI. + */ + if (mode->clock >= 165000 && + nv_encoder->dcb->duallink_possible && + !drm_detect_hdmi_monitor(nv_connector->edid)) + proto |= 0x4; } else { proto = 0x2; } diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c index f0d96e5da6b4..3695ccce68c7 100644 --- a/drivers/gpu/drm/nouveau/nv50_fence.c +++ b/drivers/gpu/drm/nouveau/nv50_fence.c @@ -24,6 +24,7 @@ #include <nvif/os.h> #include <nvif/class.h> +#include <nvif/cl0002.h> #include "nouveau_drm.h" #include "nouveau_dma.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index 297e1e953fa6..e1943910858e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -28,6 +28,7 @@ #include <nvif/class.h> #include <nvif/event.h> +#include <nvif/if0000.h> #include <nvif/unpack.h> struct nvkm_client_notify { @@ -96,7 +97,7 @@ nvkm_client_notify_new(struct nvkm_object *object, struct nvif_notify_req_v0 v0; } *req = data; u8 index, reply; - int ret; + int ret = -ENOSYS; for (index = 0; index < ARRAY_SIZE(client->notify); index++) { if (!client->notify[index]) @@ -111,7 +112,7 @@ nvkm_client_notify_new(struct nvkm_object *object, return -ENOMEM; nvif_ioctl(object, "notify new size %d\n", size); - if (nvif_unpack(req->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, true))) { nvif_ioctl(object, "notify new vers %d reply %d route %02x " "token %llx\n", req->v0.version, req->v0.reply, req->v0.route, req->v0.token); @@ -143,10 +144,10 @@ nvkm_client_mthd_devlist(struct nvkm_object *object, void *data, u32 size) union { struct nv_client_devlist_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "client devlist size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(object, "client devlist vers %d count %d\n", args->v0.version, args->v0.count); if (size == sizeof(args->v0.device[0]) * args->v0.count) { diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index d87d6ab03cc7..b0db51847c36 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -34,10 +34,10 @@ nvkm_ioctl_nop(struct nvkm_object *object, void *data, u32 size) union { struct nvif_ioctl_nop_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "nop size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "nop vers %lld\n", args->v0.version); args->v0.version = NVIF_VERSION_LATEST; } @@ -52,10 +52,10 @@ nvkm_ioctl_sclass(struct nvkm_object *object, void *data, u32 size) struct nvif_ioctl_sclass_v0 v0; } *args = data; struct nvkm_oclass oclass; - int ret, i = 0; + int ret = -ENOSYS, i = 0; nvif_ioctl(object, "sclass size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(object, "sclass vers %d count %d\n", args->v0.version, args->v0.count); if (size != args->v0.count * sizeof(args->v0.oclass[0])) @@ -86,10 +86,10 @@ nvkm_ioctl_new(struct nvkm_object *parent, void *data, u32 size) struct nvkm_client *client = parent->client; struct nvkm_object *object = NULL; struct nvkm_oclass oclass; - int ret, i = 0; + int ret = -ENOSYS, i = 0; nvif_ioctl(parent, "new size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(parent, "new vers %d handle %08x class %08x " "route %02x token %llx object %016llx\n", args->v0.version, args->v0.handle, args->v0.oclass, @@ -147,10 +147,10 @@ nvkm_ioctl_del(struct nvkm_object *object, void *data, u32 size) union { struct nvif_ioctl_del none; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "delete size %d\n", size); - if (nvif_unvers(args->none)) { + if (!(ret = nvif_unvers(ret, &data, &size, args->none))) { nvif_ioctl(object, "delete\n"); nvkm_object_fini(object, false); nvkm_object_del(&object); @@ -165,10 +165,10 @@ nvkm_ioctl_mthd(struct nvkm_object *object, void *data, u32 size) union { struct nvif_ioctl_mthd_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "mthd size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(object, "mthd vers %d mthd %02x\n", args->v0.version, args->v0.method); ret = nvkm_object_mthd(object, args->v0.method, data, size); @@ -189,10 +189,10 @@ nvkm_ioctl_rd(struct nvkm_object *object, void *data, u32 size) u16 b16; u32 b32; } v; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "rd size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "rd vers %d size %d addr %016llx\n", args->v0.version, args->v0.size, args->v0.addr); switch (args->v0.size) { @@ -223,10 +223,10 @@ nvkm_ioctl_wr(struct nvkm_object *object, void *data, u32 size) union { struct nvif_ioctl_wr_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "wr size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "wr vers %d size %d addr %016llx data %08x\n", args->v0.version, args->v0.size, args->v0.addr, @@ -251,10 +251,10 @@ nvkm_ioctl_map(struct nvkm_object *object, void *data, u32 size) union { struct nvif_ioctl_map_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "map size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "map vers %d\n", args->v0.version); ret = nvkm_object_map(object, &args->v0.handle, &args->v0.length); @@ -269,10 +269,10 @@ nvkm_ioctl_unmap(struct nvkm_object *object, void *data, u32 size) union { struct nvif_ioctl_unmap none; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "unmap size %d\n", size); - if (nvif_unvers(args->none)) { + if (!(ret = nvif_unvers(ret, &data, &size, args->none))) { nvif_ioctl(object, "unmap\n"); } @@ -286,10 +286,10 @@ nvkm_ioctl_ntfy_new(struct nvkm_object *object, void *data, u32 size) struct nvif_ioctl_ntfy_new_v0 v0; } *args = data; struct nvkm_event *event; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "ntfy new size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(object, "ntfy new vers %d event %02x\n", args->v0.version, args->v0.event); ret = nvkm_object_ntfy(object, args->v0.event, &event); @@ -312,10 +312,10 @@ nvkm_ioctl_ntfy_del(struct nvkm_object *object, void *data, u32 size) union { struct nvif_ioctl_ntfy_del_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "ntfy del size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "ntfy del vers %d index %d\n", args->v0.version, args->v0.index); ret = nvkm_client_notify_del(client, args->v0.index); @@ -331,10 +331,10 @@ nvkm_ioctl_ntfy_get(struct nvkm_object *object, void *data, u32 size) union { struct nvif_ioctl_ntfy_get_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "ntfy get size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "ntfy get vers %d index %d\n", args->v0.version, args->v0.index); ret = nvkm_client_notify_get(client, args->v0.index); @@ -350,10 +350,10 @@ nvkm_ioctl_ntfy_put(struct nvkm_object *object, void *data, u32 size) union { struct nvif_ioctl_ntfy_put_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "ntfy put size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "ntfy put vers %d index %d\n", args->v0.version, args->v0.index); ret = nvkm_client_notify_put(client, args->v0.index); @@ -421,12 +421,12 @@ nvkm_ioctl(struct nvkm_client *client, bool supervisor, union { struct nvif_ioctl_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; client->super = supervisor; nvif_ioctl(object, "size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(object, "vers %d type %02x object %016llx owner %02x\n", args->v0.version, args->v0.type, args->v0.object, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c index c541a1c012dc..e2b944dce9b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c @@ -22,19 +22,65 @@ * Authors: Ben Skeggs */ #include "priv.h" +#include <core/enum.h> #include <nvif/class.h> +static const struct nvkm_enum +gk104_ce_launcherr_report[] = { + { 0x0, "NO_ERR" }, + { 0x1, "2D_LAYER_EXCEEDS_DEPTH" }, + { 0x2, "INVALID_ARGUMENT" }, + { 0x3, "MEM2MEM_RECT_OUT_OF_BOUNDS" }, + { 0x4, "SRC_LINE_EXCEEDS_PITCH" }, + { 0x5, "SRC_LINE_EXCEEDS_NEG_PITCH" }, + { 0x6, "DST_LINE_EXCEEDS_PITCH" }, + { 0x7, "DST_LINE_EXCEEDS_NEG_PITCH" }, + { 0x8, "BAD_SRC_PIXEL_COMP_REF" }, + { 0x9, "INVALID_VALUE" }, + { 0xa, "UNUSED_FIELD" }, + { 0xb, "INVALID_OPERATION" }, + {} +}; + +static void +gk104_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) +{ + struct nvkm_subdev *subdev = &ce->subdev; + struct nvkm_device *device = subdev->device; + u32 stat = nvkm_rd32(device, 0x104f14 + base); + const struct nvkm_enum *en = + nvkm_enum_find(gk104_ce_launcherr_report, stat & 0x0000000f); + nvkm_warn(subdev, "LAUNCHERR %08x [%s]\n", stat, en ? en->name : ""); + nvkm_wr32(device, 0x104f14 + base, 0x00000000); +} + void gk104_ce_intr(struct nvkm_engine *ce) { const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x1000; struct nvkm_subdev *subdev = &ce->subdev; struct nvkm_device *device = subdev->device; - u32 stat = nvkm_rd32(device, 0x104908 + base); - if (stat) { - nvkm_warn(subdev, "intr %08x\n", stat); - nvkm_wr32(device, 0x104908 + base, stat); + u32 mask = nvkm_rd32(device, 0x104904 + base); + u32 intr = nvkm_rd32(device, 0x104908 + base) & mask; + if (intr & 0x00000001) { + nvkm_warn(subdev, "BLOCKPIPE\n"); + nvkm_wr32(device, 0x104908 + base, 0x00000001); + intr &= ~0x00000001; + } + if (intr & 0x00000002) { + nvkm_warn(subdev, "NONBLOCKPIPE\n"); + nvkm_wr32(device, 0x104908 + base, 0x00000002); + intr &= ~0x00000002; + } + if (intr & 0x00000004) { + gk104_ce_intr_launcherr(ce, base); + nvkm_wr32(device, 0x104908 + base, 0x00000004); + intr &= ~0x00000004; + } + if (intr) { + nvkm_warn(subdev, "intr %08x\n", intr); + nvkm_wr32(device, 0x104908 + base, intr); } } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index bbc9824af6e0..b1ba1c782a2b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1388,7 +1388,7 @@ nvc1_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gf106_pci_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1423,7 +1423,7 @@ nvc3_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gf106_pci_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1566,7 +1566,7 @@ nvcf_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gf106_pci_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1601,7 +1601,7 @@ nvd7_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gf106_pci_new, .therm = gf119_therm_new, .timer = nv41_timer_new, .ce[0] = gf100_ce_new, @@ -1634,7 +1634,7 @@ nvd9_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gf106_pci_new, .pmu = gf119_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, @@ -1669,7 +1669,7 @@ nve4_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, @@ -1706,7 +1706,7 @@ nve6_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, @@ -1743,7 +1743,7 @@ nve7_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, @@ -1804,7 +1804,7 @@ nvf0_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, @@ -1840,7 +1840,7 @@ nvf1_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, @@ -1876,7 +1876,7 @@ nv106_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gk208_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, @@ -1912,7 +1912,7 @@ nv108_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gk208_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, @@ -1948,7 +1948,7 @@ nv117_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gm107_pmu_new, .therm = gm107_therm_new, .timer = gk20a_timer_new, @@ -1973,13 +1973,13 @@ nv124_chipset = { .fuse = gm107_fuse_new, .gpio = gk104_gpio_new, .i2c = gm204_i2c_new, - .ibus = gk104_ibus_new, + .ibus = gm204_ibus_new, .imem = nv50_instmem_new, - .ltc = gm107_ltc_new, + .ltc = gm204_ltc_new, .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gm107_pmu_new, .timer = gk20a_timer_new, .volt = gk104_volt_new, @@ -2004,13 +2004,13 @@ nv126_chipset = { .fuse = gm107_fuse_new, .gpio = gk104_gpio_new, .i2c = gm204_i2c_new, - .ibus = gk104_ibus_new, + .ibus = gm204_ibus_new, .imem = nv50_instmem_new, - .ltc = gm107_ltc_new, + .ltc = gm204_ltc_new, .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = gk104_pci_new, .pmu = gm107_pmu_new, .timer = gk20a_timer_new, .volt = gk104_volt_new, @@ -2033,7 +2033,7 @@ nv12b_chipset = { .fuse = gm107_fuse_new, .ibus = gk20a_ibus_new, .imem = gk20a_instmem_new, - .ltc = gm107_ltc_new, + .ltc = gm204_ltc_new, .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .timer = gk20a_timer_new, @@ -2494,7 +2494,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func, device->pri = ioremap(mmio_base, mmio_size); if (!device->pri) { nvdev_error(device, "unable to map PRI\n"); - return -ENOMEM; + ret = -ENOMEM; + goto done; } } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c index cf8bc068e9b7..b0ece71aefde 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c @@ -27,6 +27,7 @@ #include <subdev/clk.h> #include <nvif/class.h> +#include <nvif/if0001.h> #include <nvif/ioctl.h> #include <nvif/unpack.h> @@ -37,10 +38,10 @@ nvkm_control_mthd_pstate_info(struct nvkm_control *ctrl, void *data, u32 size) struct nvif_control_pstate_info_v0 v0; } *args = data; struct nvkm_clk *clk = ctrl->device->clk; - int ret; + int ret = -ENOSYS; nvif_ioctl(&ctrl->object, "control pstate info size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(&ctrl->object, "control pstate info vers %d\n", args->v0.version); } else @@ -75,10 +76,10 @@ nvkm_control_mthd_pstate_attr(struct nvkm_control *ctrl, void *data, u32 size) struct nvkm_cstate *cstate; int i = 0, j = -1; u32 lo, hi; - int ret; + int ret = -ENOSYS; nvif_ioctl(&ctrl->object, "control pstate attr size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(&ctrl->object, "control pstate attr vers %d state %d index %d\n", args->v0.version, args->v0.state, args->v0.index); @@ -143,10 +144,10 @@ nvkm_control_mthd_pstate_user(struct nvkm_control *ctrl, void *data, u32 size) struct nvif_control_pstate_user_v0 v0; } *args = data; struct nvkm_clk *clk = ctrl->device->clk; - int ret; + int ret = -ENOSYS; nvif_ioctl(&ctrl->object, "control pstate user size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(&ctrl->object, "control pstate user vers %d ustate %d pwrsrc %d\n", args->v0.version, args->v0.ustate, args->v0.pwrsrc); @@ -204,7 +205,7 @@ nvkm_control_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, const struct nvkm_device_oclass nvkm_control_oclass = { - .base.oclass = NVIF_IOCTL_NEW_V0_CONTROL, + .base.oclass = NVIF_CLASS_CONTROL, .base.minver = -1, .base.maxver = -1, .ctor = nvkm_control_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index 1ae48f27029d..137066426ed7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -31,6 +31,7 @@ #include <subdev/timer.h> #include <nvif/class.h> +#include <nvif/cl0080.h> #include <nvif/unpack.h> struct nvkm_udevice { @@ -48,10 +49,10 @@ nvkm_udevice_info(struct nvkm_udevice *udev, void *data, u32 size) union { struct nv_device_info_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "device info size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "device info vers %d\n", args->v0.version); } else return ret; @@ -123,13 +124,16 @@ nvkm_udevice_info(struct nvkm_udevice *udev, void *data, u32 size) static int nvkm_udevice_time(struct nvkm_udevice *udev, void *data, u32 size) { + struct nvkm_object *object = &udev->object; struct nvkm_device *device = udev->device; union { struct nv_device_time_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(object, "device time size %d\n", size); + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { + nvif_ioctl(object, "device time vers %d\n", args->v0.version); args->v0.time = nvkm_timer_read(device->timer); } @@ -140,6 +144,7 @@ static int nvkm_udevice_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { struct nvkm_udevice *udev = nvkm_udevice(object); + nvif_ioctl(object, "device mthd %08x\n", mthd); switch (mthd) { case NV_DEVICE_V0_INFO: return nvkm_udevice_info(udev, data, size); @@ -331,10 +336,10 @@ nvkm_udevice_new(const struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object *parent = &client->object; const struct nvkm_object_func *func; struct nvkm_udevice *udev; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create device size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create device v%d device %016llx\n", args->v0.version, args->v0.device); } else diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c index 44b67719f64d..785fa76d0fbf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c @@ -32,6 +32,7 @@ #include <subdev/bios/dcb.h> #include <nvif/class.h> +#include <nvif/cl0046.h> #include <nvif/event.h> #include <nvif/unpack.h> @@ -58,9 +59,9 @@ nvkm_disp_vblank_ctor(struct nvkm_object *object, void *data, u32 size, union { struct nvif_notify_head_req_v0 v0; } *req = data; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(req->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, false))) { notify->size = sizeof(struct nvif_notify_head_rep_v0); if (ret = -ENXIO, req->v0.head <= disp->vblank.index_nr) { notify->types = 1; @@ -96,9 +97,9 @@ nvkm_disp_hpd_ctor(struct nvkm_object *object, void *data, u32 size, struct nvif_notify_conn_req_v0 v0; } *req = data; struct nvkm_output *outp; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(req->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, req->v0, 0, 0, false))) { notify->size = sizeof(struct nvif_notify_conn_rep_v0); list_for_each_entry(outp, &disp->outp, head) { if (ret = -ENXIO, outp->conn->index == req->v0.conn) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c index 1fd89edefc26..83f152300ec0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c @@ -27,6 +27,7 @@ #include <core/client.h> #include <nvif/class.h> +#include <nvif/cl507c.h> #include <nvif/unpack.h> int @@ -41,11 +42,11 @@ nv50_disp_base_new(const struct nv50_disp_dmac_func *func, } *args = data; struct nvkm_object *parent = oclass->parent; struct nv50_disp *disp = root->disp; - int head, ret; + int head, ret = -ENOSYS; u64 push; nvif_ioctl(parent, "create disp base channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create disp base channel dma vers %d " "pushbuf %016llx head %d\n", args->v0.version, args->v0.pushbuf, args->v0.head); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c index 01803c0679b6..dd2953bc9264 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c @@ -28,7 +28,7 @@ #include <core/ramht.h> #include <engine/dma.h> -#include <nvif/class.h> +#include <nvif/cl507d.h> #include <nvif/event.h> #include <nvif/unpack.h> @@ -134,9 +134,9 @@ nv50_disp_chan_uevent_ctor(struct nvkm_object *object, void *data, u32 size, union { struct nvif_notify_uevent_req none; } *args = data; - int ret; + int ret = -ENOSYS; - if (nvif_unvers(args->none)) { + if (!(ret = nvif_unvers(ret, &data, &size, args->none))) { notify->size = sizeof(struct nvif_notify_uevent_rep); notify->types = 1; notify->index = chan->chid; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c index db4a9b3e0e09..b547c8b833ca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c @@ -28,6 +28,7 @@ #include <subdev/timer.h> #include <nvif/class.h> +#include <nvif/cl507d.h> #include <nvif/unpack.h> int @@ -42,10 +43,10 @@ nv50_disp_core_new(const struct nv50_disp_dmac_func *func, } *args = data; struct nvkm_object *parent = oclass->parent; u64 push; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create disp core channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create disp core channel dma vers %d " "pushbuf %016llx\n", args->v0.version, args->v0.pushbuf); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c index 225858e62cf6..8b1320499a0f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c @@ -27,6 +27,7 @@ #include <core/client.h> #include <nvif/class.h> +#include <nvif/cl507a.h> #include <nvif/unpack.h> int @@ -41,10 +42,10 @@ nv50_disp_curs_new(const struct nv50_disp_chan_func *func, } *args = data; struct nvkm_object *parent = oclass->parent; struct nv50_disp *disp = root->disp; - int head, ret; + int head, ret = -ENOSYS; nvif_ioctl(parent, "create disp cursor size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create disp cursor vers %d head %d\n", args->v0.version, args->v0.head); if (args->v0.head > disp->base.head.nr) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c index 9bfa9e7dc161..c9b78b8f9c87 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c @@ -27,7 +27,7 @@ #include <core/client.h> #include <subdev/timer.h> -#include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -39,10 +39,10 @@ nv50_dac_power(NV50_DISP_MTHD_V1) struct nv50_disp_dac_pwr_v0 v0; } *args = data; u32 stat; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp dac pwr size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp dac pwr vers %d state %d data %d " "vsync %d hsync %d\n", args->v0.version, args->v0.state, args->v0.data, @@ -76,10 +76,10 @@ nv50_dac_sense(NV50_DISP_MTHD_V1) } *args = data; const u32 doff = outp->or * 0x800; u32 loadval; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp dac load size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp dac load vers %d data %08x\n", args->v0.version, args->v0.data); if (args->v0.data & 0xfff00000) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c index 186fd3ac78f6..f0314664349c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c @@ -158,7 +158,7 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) switch (outp->info.type) { case DCB_OUTPUT_TMDS: *conf = (ctrl & 0x00000f00) >> 8; - if (pclk >= 165000) + if (*conf == 5) *conf |= 0x0100; break; case DCB_OUTPUT_LVDS: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c index af99efbd63f7..da6129b2b78f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c @@ -29,7 +29,7 @@ #include <subdev/bios/dcb.h> #include <subdev/timer.h> -#include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -41,10 +41,10 @@ gf119_hda_eld(NV50_DISP_MTHD_V1) } *args = data; const u32 soff = outp->or * 0x030; const u32 hoff = head * 0x800; - int ret, i; + int ret = -ENOSYS, i; nvif_ioctl(object, "disp sor hda eld size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version); if (size > 0x60) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c index c1590b746f13..6f0436df0219 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c @@ -27,7 +27,7 @@ #include <core/client.h> #include <subdev/timer.h> -#include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -38,10 +38,10 @@ gt215_hda_eld(NV50_DISP_MTHD_V1) struct nv50_disp_sor_hda_eld_v0 v0; } *args = data; const u32 soff = outp->or * 0x800; - int ret, i; + int ret = -ENOSYS, i; nvif_ioctl(object, "disp sor hda eld size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version); if (size > 0x60) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c index ee9e800a8f06..1c4256e8cbd6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c @@ -25,7 +25,7 @@ #include <core/client.h> -#include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -37,10 +37,10 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1) struct nv50_disp_sor_hdmi_pwr_v0 v0; } *args = data; u32 ctrl; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp sor hdmi ctrl size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp sor hdmi ctrl vers %d state %d " "max_ac_packet %d rekey %d\n", args->v0.version, args->v0.state, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c index b5af025d3b04..632f02da1382 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c @@ -25,7 +25,7 @@ #include <core/client.h> -#include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -37,10 +37,10 @@ gf119_hdmi_ctrl(NV50_DISP_MTHD_V1) struct nv50_disp_sor_hdmi_pwr_v0 v0; } *args = data; u32 ctrl; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp sor hdmi ctrl size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp sor hdmi ctrl vers %d state %d " "max_ac_packet %d rekey %d\n", args->v0.version, args->v0.state, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c index 110dc19e4f67..4e8067d511d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c @@ -25,7 +25,7 @@ #include <core/client.h> -#include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -38,10 +38,10 @@ gk104_hdmi_ctrl(NV50_DISP_MTHD_V1) struct nv50_disp_sor_hdmi_pwr_v0 v0; } *args = data; u32 ctrl; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp sor hdmi ctrl size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp sor hdmi ctrl vers %d state %d " "max_ac_packet %d rekey %d\n", args->v0.version, args->v0.state, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c index 61237dbfa35a..f1afc16494b6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c @@ -26,7 +26,7 @@ #include <core/client.h> -#include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -38,10 +38,10 @@ gt215_hdmi_ctrl(NV50_DISP_MTHD_V1) struct nv50_disp_sor_hdmi_pwr_v0 v0; } *args = data; u32 ctrl; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp sor hdmi ctrl size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp sor hdmi ctrl vers %d state %d " "max_ac_packet %d rekey %d\n", args->v0.version, args->v0.state, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c index 32e73a975b58..4226d2153b9c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c @@ -391,7 +391,7 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) switch (outp->info.type) { case DCB_OUTPUT_TMDS: *conf = (ctrl & 0x00000f00) >> 8; - if (pclk >= 165000) + if (*conf == 5) *conf |= 0x0100; break; case DCB_OUTPUT_LVDS: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c index cd888a1e443c..3940b9c966ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c @@ -27,6 +27,7 @@ #include <core/client.h> #include <nvif/class.h> +#include <nvif/cl507b.h> #include <nvif/unpack.h> int @@ -41,10 +42,10 @@ nv50_disp_oimm_new(const struct nv50_disp_chan_func *func, } *args = data; struct nvkm_object *parent = oclass->parent; struct nv50_disp *disp = root->disp; - int head, ret; + int head, ret = -ENOSYS; nvif_ioctl(parent, "create disp overlay size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create disp overlay vers %d head %d\n", args->v0.version, args->v0.head); if (args->v0.head > disp->base.head.nr) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c index 6fa296c047b8..2a49c46425cd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c @@ -27,6 +27,7 @@ #include <core/client.h> #include <nvif/class.h> +#include <nvif/cl507e.h> #include <nvif/unpack.h> int @@ -41,11 +42,11 @@ nv50_disp_ovly_new(const struct nv50_disp_dmac_func *func, } *args = data; struct nvkm_object *parent = oclass->parent; struct nv50_disp *disp = root->disp; - int head, ret; + int head, ret = -ENOSYS; u64 push; nvif_ioctl(parent, "create disp overlay channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create disp overlay channel dma vers %d " "pushbuf %016llx head %d\n", args->v0.version, args->v0.pushbuf, args->v0.head); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c index ab524bde7795..6c532eadba17 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c @@ -28,7 +28,7 @@ #include <subdev/i2c.h> #include <subdev/timer.h> -#include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -40,10 +40,10 @@ nv50_pior_power(NV50_DISP_MTHD_V1) struct nv50_disp_pior_pwr_v0 v0; } *args = data; u32 ctrl, type; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp pior pwr size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp pior pwr vers %d state %d type %x\n", args->v0.version, args->v0.state, args->v0.type); if (args->v0.type > 0x0f) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c index 8591726871ac..335d88823c22 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c @@ -29,6 +29,7 @@ #include <subdev/timer.h> #include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -39,12 +40,12 @@ gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0) const u32 blanke = nvkm_rd32(device, 0x64041c + (head * 0x300)); const u32 blanks = nvkm_rd32(device, 0x640420 + (head * 0x300)); union { - struct nv04_disp_scanoutpos_v0 v0; + struct nv50_disp_scanoutpos_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp scanoutpos size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); args->v0.vblanke = (blanke & 0xffff0000) >> 16; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c index 2be846374d39..f535f43231e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c @@ -27,6 +27,7 @@ #include <core/client.h> #include <nvif/class.h> +#include <nvif/cl0046.h> #include <nvif/unpack.h> struct nv04_disp_root { @@ -45,10 +46,10 @@ nv04_disp_scanoutpos(struct nv04_disp_root *root, struct nv04_disp_scanoutpos_v0 v0; } *args = data; u32 line; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp scanoutpos size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); args->v0.vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0xffff; @@ -85,10 +86,10 @@ nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) union { struct nv04_disp_mthd_v0 v0; } *args = data; - int head, ret; + int head, ret = -ENOSYS; nvif_ioctl(object, "disp mthd size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(object, "disp mthd vers %d mthd %02x head %d\n", args->v0.version, args->v0.method, args->v0.head); mthd = args->v0.method; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c index 06fb24d88702..2f9cecd81d04 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c @@ -29,6 +29,7 @@ #include <subdev/timer.h> #include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -39,12 +40,12 @@ nv50_disp_root_scanoutpos(NV50_DISP_MTHD_V0) const u32 blanks = nvkm_rd32(device, 0x610af4 + (head * 0x540)); const u32 total = nvkm_rd32(device, 0x610afc + (head * 0x540)); union { - struct nv04_disp_scanoutpos_v0 v0; + struct nv50_disp_scanoutpos_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp scanoutpos size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); args->v0.vblanke = (blanke & 0xffff0000) >> 16; @@ -78,19 +79,19 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) struct nvkm_output *outp = NULL; struct nvkm_output *temp; u16 type, mask = 0; - int head, ret; + int head, ret = -ENOSYS; if (mthd != NV50_DISP_MTHD) return -EINVAL; nvif_ioctl(object, "disp mthd size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(object, "disp mthd vers %d mthd %02x head %d\n", args->v0.version, args->v0.method, args->v0.head); mthd = args->v0.method; head = args->v0.head; } else - if (nvif_unpack(args->v1, 1, 1, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v1, 1, 1, true))) { nvif_ioctl(object, "disp mthd vers %d mthd %02x " "type %04x mask %04x\n", args->v1.version, args->v1.method, @@ -143,8 +144,9 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) union { struct nv50_disp_sor_lvds_script_v0 v0; } *args = data; + int ret = -ENOSYS; nvif_ioctl(object, "disp sor lvds script size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp sor lvds script " "vers %d name %04x\n", args->v0.version, args->v0.script); @@ -159,8 +161,9 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) union { struct nv50_disp_sor_dp_pwr_v0 v0; } *args = data; + int ret = -ENOSYS; nvif_ioctl(object, "disp sor dp pwr size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp sor dp pwr vers %d state %d\n", args->v0.version, args->v0.state); if (args->v0.state == 0) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c index 29e0d2a9a839..53596bed3c36 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c @@ -27,7 +27,7 @@ #include <core/client.h> #include <subdev/timer.h> -#include <nvif/class.h> +#include <nvif/cl5070.h> #include <nvif/unpack.h> int @@ -39,10 +39,10 @@ nv50_sor_power(NV50_DISP_MTHD_V1) } *args = data; const u32 soff = outp->or * 0x800; u32 stat; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "disp sor pwr size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "disp sor pwr vers %d state %d\n", args->v0.version, args->v0.state); stat = !!args->v0.state; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c index 45ab062661a4..13c661b1ef14 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c @@ -28,7 +28,7 @@ #include <subdev/fb.h> #include <subdev/instmem.h> -#include <nvif/class.h> +#include <nvif/cl0002.h> #include <nvif/unpack.h> static int @@ -69,7 +69,7 @@ nvkm_dmaobj_ctor(const struct nvkm_dmaobj_func *func, struct nvkm_dma *dma, struct nvkm_fb *fb = device->fb; void *data = *pdata; u32 size = *psize; - int ret; + int ret = -ENOSYS; nvkm_object_ctor(&nvkm_dmaobj_func, oclass, &dmaobj->object); dmaobj->func = func; @@ -77,7 +77,7 @@ nvkm_dmaobj_ctor(const struct nvkm_dmaobj_func *func, struct nvkm_dma *dma, RB_CLEAR_NODE(&dmaobj->rb); nvif_ioctl(parent, "create dma size %d\n", *psize); - if (nvif_unpack(args->v0, 0, 0, true)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { nvif_ioctl(parent, "create dma vers %d target %d access %d " "start %016llx limit %016llx\n", args->v0.version, args->v0.target, args->v0.access, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c index 13e341cc4e32..ef7ac360101e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c @@ -28,7 +28,7 @@ #include <core/gpuobj.h> #include <subdev/fb.h> -#include <nvif/class.h> +#include <nvif/cl0002.h> #include <nvif/unpack.h> struct gf100_dmaobj { @@ -87,10 +87,11 @@ gf100_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, if (ret) return ret; + ret = -ENOSYS; args = data; nvif_ioctl(parent, "create gf100 dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create gf100 dma vers %d priv %d kind %02x\n", args->v0.version, args->v0.priv, args->v0.kind); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c index 0e1af8b4db84..c068cee34588 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c @@ -28,7 +28,7 @@ #include <core/gpuobj.h> #include <subdev/fb.h> -#include <nvif/class.h> +#include <nvif/cl0002.h> #include <nvif/unpack.h> struct gf119_dmaobj { @@ -85,10 +85,11 @@ gf119_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, if (ret) return ret; + ret = -ENOSYS; args = data; nvif_ioctl(parent, "create gf119 dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create gf100 dma vers %d page %d kind %02x\n", args->v0.version, args->v0.page, args->v0.kind); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c index 5b7ce313ea14..6a85b5dea643 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c @@ -28,7 +28,7 @@ #include <core/gpuobj.h> #include <subdev/fb.h> -#include <nvif/class.h> +#include <nvif/cl0002.h> #include <nvif/unpack.h> struct nv50_dmaobj { @@ -87,10 +87,11 @@ nv50_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, if (ret) return ret; + ret = -ENOSYS; args = data; nvif_ioctl(parent, "create nv50 dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create nv50 dma vers %d priv %d part %d " "comp %d kind %02x\n", args->v0.version, args->v0.priv, args->v0.part, args->v0.comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index 1fbbfbe6ca9c..cfc7d5725a61 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -129,9 +129,9 @@ nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size, union { struct nvif_notify_uevent_req none; } *req = data; - int ret; + int ret = -ENOSYS; - if (nvif_unvers(req->none)) { + if (!(ret = nvif_unvers(ret, &data, &size, req->none))) { notify->size = sizeof(struct nvif_notify_uevent_rep); notify->types = 1; notify->index = 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c index 04305241ceed..aeb3387a3fb0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c @@ -28,7 +28,7 @@ #include <subdev/mmu.h> #include <subdev/timer.h> -#include <nvif/class.h> +#include <nvif/cl826e.h> int g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c index a5ca52c7b74f..caa914074752 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c @@ -27,6 +27,7 @@ #include <core/ramht.h> #include <nvif/class.h> +#include <nvif/cl826e.h> #include <nvif/unpack.h> static int @@ -35,14 +36,14 @@ g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, { struct nvkm_object *parent = oclass->parent; union { - struct nv50_channel_dma_v0 v0; + struct g82_channel_dma_v0 v0; } *args = data; struct nv50_fifo *fifo = nv50_fifo(base); struct nv50_fifo_chan *chan; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel dma vers %d vm %llx " "pushbuf %llx offset %016llx\n", args->v0.version, args->v0.vm, args->v0.pushbuf, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c index bfcc6408a772..edec30fd3ecd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c @@ -29,6 +29,7 @@ #include <subdev/instmem.h> #include <nvif/class.h> +#include <nvif/cl006b.h> #include <nvif/unpack.h> void @@ -167,10 +168,10 @@ nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, struct nv04_fifo_chan *chan = NULL; struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " "offset %08x\n", args->v0.version, args->v0.pushbuf, args->v0.offset); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c index 34f68e5bd040..f5f355ff005d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c @@ -29,6 +29,7 @@ #include <subdev/instmem.h> #include <nvif/class.h> +#include <nvif/cl006b.h> #include <nvif/unpack.h> static int @@ -43,10 +44,10 @@ nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, struct nv04_fifo_chan *chan = NULL; struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " "offset %08x\n", args->v0.version, args->v0.pushbuf, args->v0.offset); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c index ed7cc9f2b540..7edc6a564b5d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c @@ -29,6 +29,7 @@ #include <subdev/instmem.h> #include <nvif/class.h> +#include <nvif/cl006b.h> #include <nvif/unpack.h> static int @@ -43,10 +44,10 @@ nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, struct nv04_fifo_chan *chan = NULL; struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " "offset %08x\n", args->v0.version, args->v0.pushbuf, args->v0.offset); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c index 043b6c325949..0ec179fc40a1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c @@ -29,6 +29,7 @@ #include <subdev/instmem.h> #include <nvif/class.h> +#include <nvif/cl006b.h> #include <nvif/unpack.h> static bool @@ -188,10 +189,10 @@ nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, struct nv04_fifo_chan *chan = NULL; struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " "offset %08x\n", args->v0.version, args->v0.pushbuf, args->v0.offset); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c index 6b3b15f12c39..480bc3777be5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c @@ -27,6 +27,7 @@ #include <core/ramht.h> #include <nvif/class.h> +#include <nvif/cl506e.h> #include <nvif/unpack.h> static int @@ -39,10 +40,10 @@ nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, } *args = data; struct nv50_fifo *fifo = nv50_fifo(base); struct nv50_fifo_chan *chan; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel dma vers %d vm %llx " "pushbuf %llx offset %016llx\n", args->v0.version, args->v0.vm, args->v0.pushbuf, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index ff6fcbda615b..36a39c7fd8d2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -47,7 +47,7 @@ gf100_fifo_uevent_fini(struct nvkm_fifo *fifo) } void -gf100_fifo_runlist_update(struct gf100_fifo *fifo) +gf100_fifo_runlist_commit(struct gf100_fifo *fifo) { struct gf100_fifo_chan *chan; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; @@ -77,6 +77,22 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo) mutex_unlock(&subdev->mutex); } +void +gf100_fifo_runlist_remove(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan) +{ + mutex_lock(&fifo->base.engine.subdev.mutex); + list_del_init(&chan->head); + mutex_unlock(&fifo->base.engine.subdev.mutex); +} + +void +gf100_fifo_runlist_insert(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan) +{ + mutex_lock(&fifo->base.engine.subdev.mutex); + list_add_tail(&chan->head, &fifo->chan); + mutex_unlock(&fifo->base.engine.subdev.mutex); +} + static inline int gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) { @@ -139,7 +155,7 @@ gf100_fifo_recover_work(struct work_struct *work) } } - gf100_fifo_runlist_update(fifo); + gf100_fifo_runlist_commit(fifo); nvkm_wr32(device, 0x00262c, engm); nvkm_mask(device, 0x002630, engm, 0x00000000); } @@ -239,7 +255,7 @@ gf100_fifo_fault_engine[] = { { 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC }, { 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 }, { 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 }, - { 0x17, "PDAEMON" }, + { 0x17, "PMU" }, {} }; @@ -270,7 +286,7 @@ gf100_fifo_fault_hubclient[] = { { 0x0c, "PMSPPP" }, { 0x0d, "PMSVLD" }, { 0x11, "PCOUNTER" }, - { 0x12, "PDAEMON" }, + { 0x12, "PMU" }, { 0x14, "CCACHE" }, { 0x15, "CCACHE_POST" }, {} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h index c649ca9b53e3..08c33c3ceaf7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h @@ -5,6 +5,7 @@ #include <subdev/mmu.h> +struct gf100_fifo_chan; struct gf100_fifo { struct nvkm_fifo base; @@ -27,5 +28,7 @@ struct gf100_fifo { }; void gf100_fifo_intr_engine(struct gf100_fifo *); -void gf100_fifo_runlist_update(struct gf100_fifo *); +void gf100_fifo_runlist_insert(struct gf100_fifo *, struct gf100_fifo_chan *); +void gf100_fifo_runlist_remove(struct gf100_fifo *, struct gf100_fifo_chan *); +void gf100_fifo_runlist_commit(struct gf100_fifo *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 98970a0b7a66..4fcd147d43c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -47,7 +47,7 @@ gk104_fifo_uevent_init(struct nvkm_fifo *fifo) } void -gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) +gk104_fifo_runlist_commit(struct gk104_fifo *fifo, u32 engine) { struct gk104_fifo_engn *engn = &fifo->engine[engine]; struct gk104_fifo_chan *chan; @@ -78,6 +78,22 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) mutex_unlock(&subdev->mutex); } +void +gk104_fifo_runlist_remove(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) +{ + mutex_lock(&fifo->base.engine.subdev.mutex); + list_del_init(&chan->head); + mutex_unlock(&fifo->base.engine.subdev.mutex); +} + +void +gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) +{ + mutex_lock(&fifo->base.engine.subdev.mutex); + list_add_tail(&chan->head, &fifo->engine[chan->engine].chan); + mutex_unlock(&fifo->base.engine.subdev.mutex); +} + static inline struct nvkm_engine * gk104_fifo_engine(struct gk104_fifo *fifo, u32 engn) { @@ -112,7 +128,7 @@ gk104_fifo_recover_work(struct work_struct *work) nvkm_subdev_fini(&engine->subdev, false); WARN_ON(nvkm_subdev_init(&engine->subdev)); } - gk104_fifo_runlist_update(fifo, gk104_fifo_subdev_engine(engn)); + gk104_fifo_runlist_commit(fifo, gk104_fifo_subdev_engine(engn)); } nvkm_wr32(device, 0x00262c, engm); @@ -180,7 +196,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) spin_lock_irqsave(&fifo->base.lock, flags); for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) { - u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); + u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); u32 busy = (stat & 0x80000000); u32 next = (stat & 0x07ff0000) >> 16; u32 chsw = (stat & 0x00008000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index 5afd9b5ec5d1..bec519d8f91e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -5,6 +5,7 @@ #include <subdev/mmu.h> +struct gk104_fifo_chan; struct gk104_fifo_engn { struct nvkm_memory *runlist[2]; int cur_runlist; @@ -35,7 +36,9 @@ void gk104_fifo_fini(struct nvkm_fifo *); void gk104_fifo_intr(struct nvkm_fifo *); void gk104_fifo_uevent_init(struct nvkm_fifo *); void gk104_fifo_uevent_fini(struct nvkm_fifo *); -void gk104_fifo_runlist_update(struct gk104_fifo *, u32 engine); +void gk104_fifo_runlist_insert(struct gk104_fifo *, struct gk104_fifo_chan *); +void gk104_fifo_runlist_remove(struct gk104_fifo *, struct gk104_fifo_chan *); +void gk104_fifo_runlist_commit(struct gk104_fifo *, u32 engine); static inline u64 gk104_fifo_engine_subdev(int engine) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c index 820132363f68..77c2f2a28bf3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c @@ -27,6 +27,7 @@ #include <core/ramht.h> #include <nvif/class.h> +#include <nvif/cl826f.h> #include <nvif/unpack.h> static int @@ -35,15 +36,15 @@ g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, { struct nvkm_object *parent = oclass->parent; union { - struct nv50_channel_gpfifo_v0 v0; + struct g82_channel_gpfifo_v0 v0; } *args = data; struct nv50_fifo *fifo = nv50_fifo(base); struct nv50_fifo_chan *chan; u64 ioffset, ilength; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create channel gpfifo size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " "pushbuf %llx ioffset %016llx " "ilength %08x\n", diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c index e7cbc139c1d4..cbc67f262322 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c @@ -29,6 +29,7 @@ #include <subdev/timer.h> #include <nvif/class.h> +#include <nvif/cl906f.h> #include <nvif/unpack.h> static u32 @@ -138,9 +139,9 @@ gf100_fifo_gpfifo_fini(struct nvkm_fifo_chan *base) u32 coff = chan->base.chid * 8; if (!list_empty(&chan->head) && !chan->killed) { - list_del_init(&chan->head); + gf100_fifo_runlist_remove(fifo, chan); nvkm_mask(device, 0x003004 + coff, 0x00000001, 0x00000000); - gf100_fifo_runlist_update(fifo); + gf100_fifo_runlist_commit(fifo); } gf100_fifo_intr_engine(fifo); @@ -160,9 +161,9 @@ gf100_fifo_gpfifo_init(struct nvkm_fifo_chan *base) nvkm_wr32(device, 0x003000 + coff, 0xc0000000 | addr); if (list_empty(&chan->head) && !chan->killed) { - list_add_tail(&chan->head, &fifo->chan); + gf100_fifo_runlist_insert(fifo, chan); nvkm_wr32(device, 0x003004 + coff, 0x001f0001); - gf100_fifo_runlist_update(fifo); + gf100_fifo_runlist_commit(fifo); } } @@ -199,10 +200,10 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, struct nvkm_object *parent = oclass->parent; struct gf100_fifo_chan *chan; u64 usermem, ioffset, ilength; - int ret, i; + int ret = -ENOSYS, i; nvif_ioctl(parent, "create channel gpfifo size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " "ioffset %016llx ilength %08x\n", args->v0.version, args->v0.vm, args->v0.ioffset, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index 0b817540a9e4..2e1df01bd928 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -30,6 +30,7 @@ #include <subdev/timer.h> #include <nvif/class.h> +#include <nvif/cla06f.h> #include <nvif/unpack.h> static int @@ -151,9 +152,9 @@ gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base) u32 coff = chan->base.chid * 8; if (!list_empty(&chan->head)) { - list_del_init(&chan->head); + gk104_fifo_runlist_remove(fifo, chan); nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800); - gk104_fifo_runlist_update(fifo, chan->engine); + gk104_fifo_runlist_commit(fifo, chan->engine); } nvkm_wr32(device, 0x800000 + coff, 0x00000000); @@ -172,9 +173,9 @@ gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base) nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr); if (list_empty(&chan->head) && !chan->killed) { - list_add_tail(&chan->head, &fifo->engine[chan->engine].chan); + gk104_fifo_runlist_insert(fifo, chan); nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400); - gk104_fifo_runlist_update(fifo, chan->engine); + gk104_fifo_runlist_commit(fifo, chan->engine); nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400); } } @@ -213,10 +214,10 @@ gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, struct gk104_fifo_chan *chan; u64 usermem, ioffset, ilength; u32 engines; - int ret, i; + int ret = -ENOSYS, i; nvif_ioctl(parent, "create channel gpfifo size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " "ioffset %016llx ilength %08x engine %08x\n", args->v0.version, args->v0.vm, args->v0.ioffset, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c index a8c69f878221..c5a7de9db259 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c @@ -27,6 +27,7 @@ #include <core/ramht.h> #include <nvif/class.h> +#include <nvif/cl506f.h> #include <nvif/unpack.h> static int @@ -40,10 +41,10 @@ nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, struct nv50_fifo *fifo = nv50_fifo(base); struct nv50_fifo_chan *chan; u64 ioffset, ilength; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create channel gpfifo size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " "pushbuf %llx ioffset %016llx " "ilength %08x\n", diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index ddaa16a71c84..ad0a6cfe7580 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -55,7 +55,7 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gk104_grctx_generate_rop_active_fbps(gr); - nvkm_mask(device, 0x5044b0, 0x8000000, 0x8000000); + nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000); gf100_gr_wait_idle(gr); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc index 7dacb3cc0668..e168b83a10c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc @@ -247,10 +247,7 @@ init: tpc_strand_info(-1); ld b32 $r4 D[$r0 + #tpc_count] - mov $r5 NV_PGRAPH_GPC0_TPC0 - ld b32 $r6 D[$r0 + #gpc_id] - shl b32 $r6 15 - add b32 $r5 $r6 + gpc_addr($r5, NV_PGRAPH_GPC0_TPC0) tpc_strand_init_tpc_loop: add b32 $r14 $r5 NV_TPC_STRAND_CNT call(nv_rd32) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h index 11bf363a6ae9..5136f9161706 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h @@ -289,7 +289,7 @@ uint32_t gm107_grgpc_code[] = { 0x020014fe, 0x12004002, 0xbd0002f6, - 0x05b34104, + 0x05ad4104, 0x400010fe, 0x00f60700, 0x0204bd00, @@ -387,180 +387,180 @@ uint32_t gm107_grgpc_code[] = { 0x7e00008f, 0x98000314, 0x00850504, - 0x06985040, - 0x0f64b604, -/* 0x04e3: tpc_strand_init_tpc_loop */ - 0xb80056bb, - 0x0005705e, - 0x0000657e, - 0x74bdf6b2, -/* 0x04f0: tpc_strand_init_idx_loop */ - 0x05605eb8, - 0x7e7fb200, - 0xb800008f, - 0x0005885e, - 0x7e082f95, - 0xb800008f, - 0x00058c5e, - 0x7e082f95, - 0xb800008f, - 0x0005905e, - 0x0000657e, - 0xb606f5b6, - 0xf4b601f0, - 0x002fbb08, - 0xb6003fbb, - 0x62b60170, - 0xbf1bf401, - 0x080050b7, - 0xf40142b6, - 0x3f0fa81b, - 0x501d608e, - 0xb201e5f0, - 0x008f7eff, - 0x8e0d0f00, - 0xf0501da8, - 0xffb201e5, - 0x00008f7e, - 0x0003147e, - 0x02010080, - 0xbd0003f6, - 0xf024bd04, - 0x00801f29, - 0x02f60230, -/* 0x0577: main */ - 0xf404bd00, - 0x28f40031, - 0x7e240d00, - 0xf4000037, - 0xe4b0f401, - 0x1d18f404, - 0x020181fe, - 0xfd20bd06, - 0xe4b60412, - 0x051efd01, - 0x7e0018fe, - 0xf400064a, -/* 0x05a6: main_not_ctx_xfer */ - 0xef94d40e, - 0x01f5f010, - 0x0002f87e, -/* 0x05b3: ih */ - 0xf9c70ef4, - 0x0188fe80, - 0x90f980f9, - 0xb0f9a0f9, - 0xe0f9d0f9, - 0x04bdf0f9, - 0xcf02004a, - 0xabc400aa, - 0x1f0bf404, - 0x004e240d, - 0x00eecf1a, - 0xcf19004f, - 0x047e00ff, - 0x010e0000, - 0xf61d0040, - 0x04bd000e, -/* 0x05f0: ih_no_fifo */ - 0xf6010040, - 0x04bd000a, - 0xe0fcf0fc, - 0xb0fcd0fc, - 0x90fca0fc, - 0x88fe80fc, - 0xf480fc00, - 0x01f80032, -/* 0x0610: hub_barrier_done */ - 0x0e98010f, - 0x04febb04, - 0x188effb2, - 0x8f7e4094, - 0x00f80000, -/* 0x0624: ctx_redswitch */ - 0x0080200f, - 0x0ff60185, - 0x0e04bd00, -/* 0x0631: ctx_redswitch_delay */ - 0x01e2b608, - 0xf1fd1bf4, - 0xf10800f5, - 0x800200f5, - 0xf6018500, - 0x04bd000f, -/* 0x064a: ctx_xfer */ - 0x008000f8, - 0x0ff60281, - 0x8e04bd00, - 0xf0501dc4, - 0xffb201e5, - 0x00008f7e, - 0x7e0711f4, -/* 0x0667: ctx_xfer_not_load */ - 0x7e000624, - 0xbd000216, - 0x47fc8024, - 0x0002f602, - 0x2cf004bd, - 0x0320b601, - 0x024afc80, - 0xbd0002f6, - 0x8e0c0f04, - 0xf0501da8, - 0xffb201e5, - 0x00008f7e, - 0x0003147e, + 0x55f05040, +/* 0x04dd: tpc_strand_init_tpc_loop */ + 0x705eb801, + 0x657e0005, + 0xf6b20000, +/* 0x04ea: tpc_strand_init_idx_loop */ + 0x5eb874bd, + 0xb2000560, + 0x008f7e7f, + 0x885eb800, + 0x2f950005, + 0x008f7e08, + 0x8c5eb800, + 0x2f950005, + 0x008f7e08, + 0x905eb800, + 0x657e0005, + 0xf5b60000, + 0x01f0b606, + 0xbb08f4b6, + 0x3fbb002f, + 0x0170b600, + 0xf40162b6, + 0x50b7bf1b, + 0x42b60800, + 0xa81bf401, 0x608e3f0f, 0xe5f0501d, 0x7effb201, 0x0f00008f, - 0x1d9c8e00, + 0x1da88e0d, 0x01e5f050, 0x8f7effb2, - 0x010f0000, - 0x0003147e, - 0xb601fcf0, - 0xa88e03f0, - 0xe5f0501d, - 0x7effb201, - 0xf000008f, - 0xa5f001ac, - 0x00008b02, - 0x040c9850, - 0xbb0fc4b6, - 0x0c9800bc, - 0x010d9800, - 0x3d7e000e, - 0xacf00001, - 0x40008b01, - 0x040c9850, - 0xbb0fc4b6, - 0x0c9800bc, - 0x020d9801, - 0x4e060f98, - 0x3d7e0800, - 0xacf00001, - 0x04a5f001, - 0x5030008b, - 0xb6040c98, - 0xbcbb0fc4, - 0x020c9800, - 0x98030d98, - 0x004e080f, - 0x013d7e02, - 0x020a7e00, - 0x03147e00, - 0x0601f400, -/* 0x073f: ctx_xfer_post */ - 0x7e1a12f4, - 0x0f000227, - 0x1da88e0d, + 0x147e0000, + 0x00800003, + 0x03f60201, + 0xbd04bd00, + 0x1f29f024, + 0x02300080, + 0xbd0002f6, +/* 0x0571: main */ + 0x0031f404, + 0x0d0028f4, + 0x00377e24, + 0xf401f400, + 0xf404e4b0, + 0x81fe1d18, + 0xbd060201, + 0x0412fd20, + 0xfd01e4b6, + 0x18fe051e, + 0x06447e00, + 0xd40ef400, +/* 0x05a0: main_not_ctx_xfer */ + 0xf010ef94, + 0xf87e01f5, + 0x0ef40002, +/* 0x05ad: ih */ + 0xfe80f9c7, + 0x80f90188, + 0xa0f990f9, + 0xd0f9b0f9, + 0xf0f9e0f9, + 0x004a04bd, + 0x00aacf02, + 0xf404abc4, + 0x240d1f0b, + 0xcf1a004e, + 0x004f00ee, + 0x00ffcf19, + 0x0000047e, + 0x0040010e, + 0x000ef61d, +/* 0x05ea: ih_no_fifo */ + 0x004004bd, + 0x000af601, + 0xf0fc04bd, + 0xd0fce0fc, + 0xa0fcb0fc, + 0x80fc90fc, + 0xfc0088fe, + 0x0032f480, +/* 0x060a: hub_barrier_done */ + 0x010f01f8, + 0xbb040e98, + 0xffb204fe, + 0x4094188e, + 0x00008f7e, +/* 0x061e: ctx_redswitch */ + 0x200f00f8, + 0x01850080, + 0xbd000ff6, +/* 0x062b: ctx_redswitch_delay */ + 0xb6080e04, + 0x1bf401e2, + 0x00f5f1fd, + 0x00f5f108, + 0x85008002, + 0x000ff601, + 0x00f804bd, +/* 0x0644: ctx_xfer */ + 0x02810080, + 0xbd000ff6, + 0x1dc48e04, + 0x01e5f050, + 0x8f7effb2, + 0x11f40000, + 0x061e7e07, +/* 0x0661: ctx_xfer_not_load */ + 0x02167e00, + 0x8024bd00, + 0xf60247fc, + 0x04bd0002, + 0xb6012cf0, + 0xfc800320, + 0x02f6024a, + 0x0f04bd00, + 0x1da88e0c, 0x01e5f050, 0x8f7effb2, 0x147e0000, -/* 0x0756: ctx_xfer_done */ - 0x107e0003, - 0x00f80006, + 0x3f0f0003, + 0x501d608e, + 0xb201e5f0, + 0x008f7eff, + 0x8e000f00, + 0xf0501d9c, + 0xffb201e5, + 0x00008f7e, + 0x147e010f, + 0xfcf00003, + 0x03f0b601, + 0x501da88e, + 0xb201e5f0, + 0x008f7eff, + 0x01acf000, + 0x8b02a5f0, + 0x98500000, + 0xc4b6040c, + 0x00bcbb0f, + 0x98000c98, + 0x000e010d, + 0x00013d7e, + 0x8b01acf0, + 0x98504000, + 0xc4b6040c, + 0x00bcbb0f, + 0x98010c98, + 0x0f98020d, + 0x08004e06, + 0x00013d7e, + 0xf001acf0, + 0x008b04a5, + 0x0c985030, + 0x0fc4b604, + 0x9800bcbb, + 0x0d98020c, + 0x080f9803, + 0x7e02004e, + 0x7e00013d, + 0x7e00020a, + 0xf4000314, + 0x12f40601, +/* 0x0739: ctx_xfer_post */ + 0x02277e1a, + 0x8e0d0f00, + 0xf0501da8, + 0xffb201e5, + 0x00008f7e, + 0x0003147e, +/* 0x0750: ctx_xfer_done */ + 0x00060a7e, + 0x000000f8, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 9f5dfc85147a..1f81069edc58 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -34,6 +34,7 @@ #include <engine/fifo.h> #include <nvif/class.h> +#include <nvif/cl9097.h> #include <nvif/unpack.h> /******************************************************************************* @@ -139,6 +140,12 @@ gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, /******************************************************************************* * Graphics object classes ******************************************************************************/ +#define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object) + +struct gf100_gr_object { + struct nvkm_object object; + struct gf100_gr_chan *chan; +}; static int gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) @@ -147,9 +154,9 @@ gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) union { struct fermi_a_zbc_color_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { switch (args->v0.format) { case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: @@ -193,9 +200,9 @@ gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) union { struct fermi_a_zbc_depth_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { switch (args->v0.format) { case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: ret = gf100_gr_zbc_depth_get(gr, args->v0.format, @@ -213,6 +220,7 @@ gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) static int gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { + nvif_ioctl(object, "fermi mthd %08x\n", mthd); switch (mthd) { case FERMI_A_ZBC_COLOR: return gf100_fermi_mthd_zbc_color(object, data, size); @@ -256,6 +264,27 @@ gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) return false; } +static const struct nvkm_object_func +gf100_gr_object_func = { +}; + +static int +gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent); + struct gf100_gr_object *object; + + if (!(object = kzalloc(sizeof(*object), GFP_KERNEL))) + return -ENOMEM; + *pobject = &object->object; + + nvkm_object_ctor(oclass->base.func ? oclass->base.func : + &gf100_gr_object_func, oclass, &object->object); + object->chan = chan; + return 0; +} + static int gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) { @@ -265,6 +294,7 @@ gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) while (gr->func->sclass[c].oclass) { if (c++ == index) { *sclass = gr->func->sclass[index]; + sclass->ctor = gf100_gr_object_new; return index; } } @@ -826,7 +856,41 @@ gf100_gr_units(struct nvkm_gr *base) return cfg; } +static const struct nvkm_bitfield gf100_dispatch_error[] = { + { 0x00000001, "INJECTED_BUNDLE_ERROR" }, + { 0x00000002, "CLASS_SUBCH_MISMATCH" }, + { 0x00000004, "SUBCHSW_DURING_NOTIFY" }, + {} +}; + +static const struct nvkm_bitfield gf100_m2mf_error[] = { + { 0x00000001, "PUSH_TOO_MUCH_DATA" }, + { 0x00000002, "PUSH_NOT_ENOUGH_DATA" }, + {} +}; + +static const struct nvkm_bitfield gf100_unk6_error[] = { + { 0x00000001, "TEMP_TOO_SMALL" }, + {} +}; + +static const struct nvkm_bitfield gf100_ccache_error[] = { + { 0x00000001, "INTR" }, + { 0x00000002, "LDCONST_OOB" }, + {} +}; + +static const struct nvkm_bitfield gf100_macro_error[] = { + { 0x00000001, "TOO_FEW_PARAMS" }, + { 0x00000002, "TOO_MANY_PARAMS" }, + { 0x00000004, "ILLEGAL_OPCODE" }, + { 0x00000008, "DOUBLE_BRANCH" }, + { 0x00000010, "WATCHDOG" }, + {} +}; + static const struct nvkm_bitfield gk104_sked_error[] = { + { 0x00000040, "CTA_RESUME" }, { 0x00000080, "CONSTANT_BUFFER_SIZE" }, { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, @@ -836,6 +900,8 @@ static const struct nvkm_bitfield gk104_sked_error[] = { { 0x00040000, "TOTAL_THREADS" }, { 0x00100000, "PROGRAM_OFFSET" }, { 0x00200000, "SHARED_MEMORY_SIZE" }, + { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" }, + { 0x01000000, "MEMORY_WINDOW_OVERLAP" }, { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, { 0x04000000, "TOTAL_REGISTER_COUNT" }, {} @@ -1005,12 +1071,16 @@ gf100_gr_trap_intr(struct gf100_gr *gr) { struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; + char error[128]; u32 trap = nvkm_rd32(device, 0x400108); int rop, gpc; if (trap & 0x00000001) { u32 stat = nvkm_rd32(device, 0x404000); - nvkm_error(subdev, "DISPATCH %08x\n", stat); + + nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error, + stat & 0x3fffffff); + nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error); nvkm_wr32(device, 0x404000, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000001); trap &= ~0x00000001; @@ -1018,7 +1088,11 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000002) { u32 stat = nvkm_rd32(device, 0x404600); - nvkm_error(subdev, "M2MF %08x\n", stat); + + nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error, + stat & 0x3fffffff); + nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error); + nvkm_wr32(device, 0x404600, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000002); trap &= ~0x00000002; @@ -1026,7 +1100,10 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000008) { u32 stat = nvkm_rd32(device, 0x408030); - nvkm_error(subdev, "CCACHE %08x\n", stat); + + nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error, + stat & 0x3fffffff); + nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error); nvkm_wr32(device, 0x408030, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000008); trap &= ~0x00000008; @@ -1034,7 +1111,8 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000010) { u32 stat = nvkm_rd32(device, 0x405840); - nvkm_error(subdev, "SHADER %08x\n", stat); + nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n", + stat, stat & 0xffffff, (stat >> 24) & 0x3f); nvkm_wr32(device, 0x405840, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000010); trap &= ~0x00000010; @@ -1042,7 +1120,11 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000040) { u32 stat = nvkm_rd32(device, 0x40601c); - nvkm_error(subdev, "UNK6 %08x\n", stat); + + nvkm_snprintbf(error, sizeof(error), gf100_unk6_error, + stat & 0x3fffffff); + nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error); + nvkm_wr32(device, 0x40601c, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000040); trap &= ~0x00000040; @@ -1050,7 +1132,16 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000080) { u32 stat = nvkm_rd32(device, 0x404490); - nvkm_error(subdev, "MACRO %08x\n", stat); + u32 pc = nvkm_rd32(device, 0x404494); + u32 op = nvkm_rd32(device, 0x40449c); + + nvkm_snprintbf(error, sizeof(error), gf100_macro_error, + stat & 0x1fffffff); + nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n", + stat, error, pc & 0x7ff, + (pc & 0x10000000) ? "" : " (invalid)", + op); + nvkm_wr32(device, 0x404490, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000080); trap &= ~0x00000080; @@ -1058,10 +1149,9 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000100) { u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; - char sked[128]; - nvkm_snprintbf(sked, sizeof(sked), gk104_sked_error, stat); - nvkm_error(subdev, "SKED: %08x [%s]\n", stat, sked); + nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat); + nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error); if (stat) nvkm_wr32(device, 0x407020, 0x40000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c index 2721592d3031..f19fabef8d73 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -27,6 +27,8 @@ #include <core/option.h> #include <nvif/class.h> +#include <nvif/if0002.h> +#include <nvif/if0003.h> #include <nvif/ioctl.h> #include <nvif/unpack.h> @@ -210,10 +212,10 @@ nvkm_perfdom_init(struct nvkm_perfdom *dom, void *data, u32 size) } *args = data; struct nvkm_object *object = &dom->object; struct nvkm_pm *pm = dom->perfmon->pm; - int ret, i; + int ret = -ENOSYS, i; nvif_ioctl(object, "perfdom init size %d\n", size); - if (nvif_unvers(args->none)) { + if (!(ret = nvif_unvers(ret, &data, &size, args->none))) { nvif_ioctl(object, "perfdom init\n"); } else return ret; @@ -240,10 +242,10 @@ nvkm_perfdom_sample(struct nvkm_perfdom *dom, void *data, u32 size) } *args = data; struct nvkm_object *object = &dom->object; struct nvkm_pm *pm = dom->perfmon->pm; - int ret; + int ret = -ENOSYS; nvif_ioctl(object, "perfdom sample size %d\n", size); - if (nvif_unvers(args->none)) { + if (!(ret = nvif_unvers(ret, &data, &size, args->none))) { nvif_ioctl(object, "perfdom sample\n"); } else return ret; @@ -264,10 +266,10 @@ nvkm_perfdom_read(struct nvkm_perfdom *dom, void *data, u32 size) } *args = data; struct nvkm_object *object = &dom->object; struct nvkm_pm *pm = dom->perfmon->pm; - int ret, i; + int ret = -ENOSYS, i; nvif_ioctl(object, "perfdom read size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "perfdom read vers %d\n", args->v0.version); } else return ret; @@ -374,10 +376,10 @@ nvkm_perfdom_new_(struct nvkm_perfmon *perfmon, struct nvkm_perfctr *ctr[4] = {}; struct nvkm_perfdom *dom; int c, s, m; - int ret; + int ret = -ENOSYS; nvif_ioctl(parent, "create perfdom size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(parent, "create perfdom vers %d dom %d mode %02x\n", args->v0.version, args->v0.domain, args->v0.mode); } else @@ -439,10 +441,10 @@ nvkm_perfmon_mthd_query_domain(struct nvkm_perfmon *perfmon, struct nvkm_pm *pm = perfmon->pm; struct nvkm_perfdom *dom; u8 domain_nr; - int di, ret; + int di, ret = -ENOSYS; nvif_ioctl(object, "perfmon query domain size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "perfmon domain vers %d iter %02x\n", args->v0.version, args->v0.iter); di = (args->v0.iter & 0xff) - 1; @@ -490,10 +492,10 @@ nvkm_perfmon_mthd_query_signal(struct nvkm_perfmon *perfmon, struct nvkm_perfsig *sig; const bool all = nvkm_boolopt(device->cfgopt, "NvPmShowAll", false); const bool raw = nvkm_boolopt(device->cfgopt, "NvPmUnnamed", all); - int ret, si; + int ret = -ENOSYS, si; nvif_ioctl(object, "perfmon query signal size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "perfmon query signal vers %d dom %d iter %04x\n", args->v0.version, args->v0.domain, args->v0.iter); @@ -543,10 +545,10 @@ nvkm_perfmon_mthd_query_source(struct nvkm_perfmon *perfmon, struct nvkm_perfsig *sig; struct nvkm_perfsrc *src; u8 source_nr = 0; - int si, ret; + int si, ret = -ENOSYS; nvif_ioctl(object, "perfmon query source size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { nvif_ioctl(object, "perfmon source vers %d dom %d sig %02x iter %02x\n", args->v0.version, args->v0.domain, args->v0.signal, @@ -612,7 +614,7 @@ nvkm_perfmon_child_get(struct nvkm_object *object, int index, struct nvkm_oclass *oclass) { if (index == 0) { - oclass->base.oclass = NVIF_IOCTL_NEW_V0_PERFDOM; + oclass->base.oclass = NVIF_CLASS_PERFDOM; oclass->base.minver = 0; oclass->base.maxver = 0; oclass->ctor = nvkm_perfmon_child_new; @@ -679,7 +681,7 @@ nvkm_pm_oclass_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, static const struct nvkm_device_oclass nvkm_pm_oclass = { - .base.oclass = NVIF_IOCTL_NEW_V0_PERFMON, + .base.oclass = NVIF_CLASS_PERFMON, .base.minver = -1, .base.maxver = -1, .ctor = nvkm_pm_oclass_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c index d082f4f73a80..f28967065639 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c @@ -53,9 +53,9 @@ nvkm_sw_chan_event_ctor(struct nvkm_object *object, void *data, u32 size, union { struct nvif_notify_uevent_req none; } *req = data; - int ret; + int ret = -ENOSYS; - if (nvif_unvers(req->none)) { + if (!(ret = nvif_unvers(ret, &data, &size, req->none))) { notify->size = sizeof(struct nvif_notify_uevent_rep); notify->types = 1; notify->index = 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c index b01ef7eca906..ea8f4247b628 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c @@ -28,8 +28,8 @@ #include <engine/disp.h> #include <engine/fifo.h> +#include <nvif/class.h> #include <nvif/event.h> -#include <nvif/ioctl.h> /******************************************************************************* * software context @@ -143,7 +143,7 @@ static const struct nvkm_sw_func gf100_sw = { .chan_new = gf100_sw_chan_new, .sclass = { - { nvkm_nvsw_new, { -1, -1, NVIF_IOCTL_NEW_V0_SW_GF100 } }, + { nvkm_nvsw_new, { -1, -1, NVIF_CLASS_SW_GF100 } }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c index 445217ffa791..b6675fe1b0ce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c @@ -27,6 +27,7 @@ #include "nvsw.h" #include <nvif/class.h> +#include <nvif/if0004.h> #include <nvif/ioctl.h> #include <nvif/unpack.h> @@ -46,9 +47,9 @@ nv04_nvsw_mthd_get_ref(struct nvkm_nvsw *nvsw, void *data, u32 size) union { struct nv04_nvsw_get_ref_v0 v0; } *args = data; - int ret; + int ret = -ENOSYS; - if (nvif_unpack(args->v0, 0, 0, false)) { + if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { args->v0.ref = atomic_read(&chan->ref); } @@ -126,7 +127,7 @@ static const struct nvkm_sw_func nv04_sw = { .chan_new = nv04_sw_chan_new, .sclass = { - { nv04_nvsw_new, { -1, -1, NVIF_IOCTL_NEW_V0_SW_NV04 } }, + { nv04_nvsw_new, { -1, -1, NVIF_CLASS_SW_NV04 } }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c index adf70d92b244..09d22fcd194c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c @@ -25,7 +25,7 @@ #include "chan.h" #include "nvsw.h" -#include <nvif/ioctl.h> +#include <nvif/class.h> /******************************************************************************* * software context @@ -56,7 +56,7 @@ static const struct nvkm_sw_func nv10_sw = { .chan_new = nv10_sw_chan_new, .sclass = { - { nvkm_nvsw_new, { -1, -1, NVIF_IOCTL_NEW_V0_SW_NV10 } }, + { nvkm_nvsw_new, { -1, -1, NVIF_CLASS_SW_NV10 } }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index a381196af69d..01573d187f2c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -28,8 +28,8 @@ #include <engine/fifo/chan.h> #include <subdev/bar.h> +#include <nvif/class.h> #include <nvif/event.h> -#include <nvif/ioctl.h> /******************************************************************************* * software context @@ -136,7 +136,7 @@ static const struct nvkm_sw_func nv50_sw = { .chan_new = nv50_sw_chan_new, .sclass = { - { nvkm_nvsw_new, { -1, -1, NVIF_IOCTL_NEW_V0_SW_NV50 } }, + { nvkm_nvsw_new, { -1, -1, NVIF_CLASS_SW_NV50 } }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c index 66cf986b9572..33dd03fff3c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c @@ -24,7 +24,7 @@ #include "nvsw.h" #include "chan.h" -#include <nvif/class.h> +#include <nvif/if0004.h> static int nvkm_nvsw_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) @@ -41,7 +41,7 @@ nvkm_nvsw_ntfy_(struct nvkm_object *object, u32 mthd, { struct nvkm_nvsw *nvsw = nvkm_nvsw(object); switch (mthd) { - case NVSW_NTFY_UEVENT: + case NV04_NVSW_NTFY_UEVENT: *pevent = &nvsw->chan->event; return 0; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c index 8304b806f2a6..a8d5d67feeaf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c @@ -143,16 +143,19 @@ dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, switch (outp->type) { case DCB_OUTPUT_DP: switch (conf & 0x00e00000) { - case 0x00000000: + case 0x00000000: /* 1.62 */ outp->dpconf.link_bw = 0x06; break; - case 0x00200000: + case 0x00200000: /* 2.7 */ outp->dpconf.link_bw = 0x0a; break; - case 0x00400000: - default: + case 0x00400000: /* 5.4 */ outp->dpconf.link_bw = 0x14; break; + case 0x00600000: /* 8.1 */ + default: + outp->dpconf.link_bw = 0x1e; + break; } switch ((conf & 0x0f000000) >> 24) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index aa7e33b42b30..636bfb665bb9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c @@ -24,6 +24,7 @@ #include <subdev/bios.h> #include <subdev/bios/bit.h> #include <subdev/bios/perf.h> +#include <subdev/pci.h> u16 nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, @@ -145,6 +146,21 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx, break; case 0x40: info->voltage = nvbios_rd08(bios, perf + 0x02); + switch (nvbios_rd08(bios, perf + 0xb) & 0x3) { + case 0: + info->pcie_speed = NVKM_PCIE_SPEED_5_0; + break; + case 3: + case 1: + info->pcie_speed = NVKM_PCIE_SPEED_2_5; + break; + case 2: + info->pcie_speed = NVKM_PCIE_SPEED_8_0; + break; + default: + break; + } + info->pcie_width = 0xff; break; default: return 0x0000; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index dc8682c91cc7..889cce2eb727 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -176,6 +176,7 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) { struct nvkm_subdev *subdev = &clk->subdev; struct nvkm_ram *ram = subdev->device->fb->ram; + struct nvkm_pci *pci = subdev->device->pci; struct nvkm_pstate *pstate; int ret, idx = 0; @@ -187,6 +188,8 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) nvkm_debug(subdev, "setting performance state %d\n", pstatei); clk->pstate = pstatei; + nvkm_pcie_set_link(pci, pstate->pcie_speed, pstate->pcie_width); + if (ram && ram->func->calc) { int khz = pstate->base.domain[nv_clk_src_mem]; do { @@ -330,6 +333,8 @@ nvkm_pstate_new(struct nvkm_clk *clk, int idx) pstate->pstate = perfE.pstate; pstate->fanspeed = perfE.fanspeed; + pstate->pcie_speed = perfE.pcie_speed; + pstate->pcie_width = perfE.pcie_width; cstate->voltage = perfE.voltage; cstate->domain[nv_clk_src_core] = perfE.core; cstate->domain[nv_clk_src_shader] = perfE.shader; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c index a52b7e7fce41..78c449b417b7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -188,7 +188,7 @@ gf100_clk_read(struct nvkm_clk *base, enum nv_clk_src src) return read_clk(clk, 0x08); case nv_clk_src_copy: return read_clk(clk, 0x09); - case nv_clk_src_daemon: + case nv_clk_src_pmu: return read_clk(clk, 0x0c); case nv_clk_src_vdec: return read_clk(clk, 0x0e); @@ -325,7 +325,7 @@ gf100_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) || - (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) || + (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) || (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec))) return ret; @@ -447,7 +447,7 @@ gf100_clk = { { nv_clk_src_rop , 0x04 }, { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, { nv_clk_src_vdec , 0x06 }, - { nv_clk_src_daemon , 0x0a }, + { nv_clk_src_pmu , 0x0a }, { nv_clk_src_hubk07 , 0x0b }, { nv_clk_src_max } } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c index 396f7e4dad0a..975c401bccab 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c @@ -209,7 +209,7 @@ gk104_clk_read(struct nvkm_clk *base, enum nv_clk_src src) return read_clk(clk, 0x07); case nv_clk_src_hubk01: return read_clk(clk, 0x08); - case nv_clk_src_daemon: + case nv_clk_src_pmu: return read_clk(clk, 0x0c); case nv_clk_src_vdec: return read_clk(clk, 0x0e); @@ -346,7 +346,7 @@ gk104_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) || (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || - (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) || + (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) || (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec))) return ret; @@ -492,7 +492,7 @@ gk104_clk = { { nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE }, { nv_clk_src_hubk01 , 0x05 }, { nv_clk_src_vdec , 0x06 }, - { nv_clk_src_daemon , 0x07 }, + { nv_clk_src_pmu , 0x07 }, { nv_clk_src_max } } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c index c233e3f653ce..056702ef69aa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c @@ -158,7 +158,7 @@ gt215_clk_read(struct nvkm_clk *base, enum nv_clk_src src) return read_clk(clk, 0x20, false); case nv_clk_src_vdec: return read_clk(clk, 0x21, false); - case nv_clk_src_daemon: + case nv_clk_src_pmu: return read_clk(clk, 0x25, false); case nv_clk_src_host: hsrc = (nvkm_rd32(device, 0xc040) & 0x30000000) >> 28; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index f5edfadb5b46..1b5fb02eab2a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -132,7 +132,7 @@ static const struct nvkm_enum vm_engine[] = { { 0x0000000b, "PCOUNTER" }, { 0x0000000c, "SEMAPHORE_BG" }, { 0x0000000d, "PCE0" }, - { 0x0000000e, "PDAEMON" }, + { 0x0000000e, "PMU" }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 9df45030ff9f..1fa3ade468ae 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -216,11 +216,11 @@ r1373f4_fini(struct gk104_ramfuc *fuc) ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16)); ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000); if (ram->mode == 2) { - ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002); - ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000); + ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000002); + ram_mask(fuc, 0x1373f4, 0x00001100, 0x00000000); } else { - ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001); - ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000); + ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001); + ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); } ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild index de888fa62b3e..7e77a7466992 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild @@ -2,3 +2,4 @@ nvkm-y += nvkm/subdev/ibus/gf100.o nvkm-y += nvkm/subdev/ibus/gf117.o nvkm-y += nvkm/subdev/ibus/gk104.o nvkm-y += nvkm/subdev/ibus/gk20a.o +nvkm-y += nvkm/subdev/ibus/gm204.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c index ba33609f643c..b5cee3f89aaa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include <subdev/ibus.h> +#include "priv.h" static void gk104_ibus_intr_hub(struct nvkm_subdev *ibus, int i) @@ -56,7 +56,7 @@ gk104_ibus_intr_gpc(struct nvkm_subdev *ibus, int i) nvkm_mask(device, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000); } -static void +void gk104_ibus_intr(struct nvkm_subdev *ibus) { struct nvkm_device *device = ibus->device; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gm204.c new file mode 100644 index 000000000000..b3839dc254ee --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gm204.c @@ -0,0 +1,40 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ +#include "priv.h" + +static const struct nvkm_subdev_func +gm204_ibus = { + .intr = gk104_ibus_intr, +}; + +int +gm204_ibus_new(struct nvkm_device *device, int index, + struct nvkm_subdev **pibus) +{ + struct nvkm_subdev *ibus; + if (!(ibus = *pibus = kzalloc(sizeof(*ibus), GFP_KERNEL))) + return -ENOMEM; + nvkm_subdev_ctor(&gm204_ibus, device, index, 0, ibus); + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h index 48e1b6365ce6..01caf798cf31 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h @@ -4,4 +4,5 @@ #include <subdev/ibus.h> void gf100_ibus_intr(struct nvkm_subdev *); +void gk104_ibus_intr(struct nvkm_subdev *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index 14107b5b7811..4c20fec64d96 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -56,7 +56,6 @@ struct gk20a_instobj { /* CPU mapping */ u32 *vaddr; - struct list_head vaddr_node; }; #define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory) @@ -66,7 +65,6 @@ struct gk20a_instobj { struct gk20a_instobj_dma { struct gk20a_instobj base; - u32 *cpuaddr; dma_addr_t handle; struct nvkm_mm_node r; }; @@ -79,6 +77,11 @@ struct gk20a_instobj_dma { struct gk20a_instobj_iommu { struct gk20a_instobj base; + /* to link into gk20a_instmem::vaddr_lru */ + struct list_head vaddr_node; + /* how many clients are using vaddr? */ + u32 use_cpt; + /* will point to the higher half of pages */ dma_addr_t *dma_addrs; /* array of base.mem->size pages (+ dma_addr_ts) */ @@ -107,8 +110,6 @@ struct gk20a_instmem { /* Only used by DMA API */ struct dma_attrs attrs; - - void __iomem * (*cpu_map)(struct nvkm_memory *); }; #define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base) @@ -130,70 +131,58 @@ gk20a_instobj_size(struct nvkm_memory *memory) return (u64)gk20a_instobj(memory)->mem.size << 12; } -static void __iomem * -gk20a_instobj_cpu_map_dma(struct nvkm_memory *memory) -{ -#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) - struct gk20a_instobj_dma *node = gk20a_instobj_dma(memory); - struct device *dev = node->base.imem->base.subdev.device->dev; - int npages = nvkm_memory_size(memory) >> 12; - struct page *pages[npages]; - int i; - - /* we shouldn't see a gk20a on anything but arm/arm64 anyways */ - /* phys_to_page does not exist on all platforms... */ - pages[0] = pfn_to_page(dma_to_phys(dev, node->handle) >> PAGE_SHIFT); - for (i = 1; i < npages; i++) - pages[i] = pages[0] + i; - - return vmap(pages, npages, VM_MAP, pgprot_writecombine(PAGE_KERNEL)); -#else - BUG(); - return NULL; -#endif -} - -static void __iomem * -gk20a_instobj_cpu_map_iommu(struct nvkm_memory *memory) +/* + * Recycle the vaddr of obj. Must be called with gk20a_instmem::lock held. + */ +static void +gk20a_instobj_iommu_recycle_vaddr(struct gk20a_instobj_iommu *obj) { - struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory); - int npages = nvkm_memory_size(memory) >> 12; - - return vmap(node->pages, npages, VM_MAP, - pgprot_writecombine(PAGE_KERNEL)); + struct gk20a_instmem *imem = obj->base.imem; + /* there should not be any user left... */ + WARN_ON(obj->use_cpt); + list_del(&obj->vaddr_node); + vunmap(obj->base.vaddr); + obj->base.vaddr = NULL; + imem->vaddr_use -= nvkm_memory_size(&obj->base.memory); + nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", imem->vaddr_use, + imem->vaddr_max); } /* - * Must be called while holding gk20a_instmem_lock + * Must be called while holding gk20a_instmem::lock */ static void gk20a_instmem_vaddr_gc(struct gk20a_instmem *imem, const u64 size) { while (imem->vaddr_use + size > imem->vaddr_max) { - struct gk20a_instobj *obj; - /* no candidate that can be unmapped, abort... */ if (list_empty(&imem->vaddr_lru)) break; - obj = list_first_entry(&imem->vaddr_lru, struct gk20a_instobj, - vaddr_node); - list_del(&obj->vaddr_node); - vunmap(obj->vaddr); - obj->vaddr = NULL; - imem->vaddr_use -= nvkm_memory_size(&obj->memory); - nvkm_debug(&imem->base.subdev, "(GC) vaddr used: %x/%x\n", - imem->vaddr_use, imem->vaddr_max); - + gk20a_instobj_iommu_recycle_vaddr( + list_first_entry(&imem->vaddr_lru, + struct gk20a_instobj_iommu, vaddr_node)); } } static void __iomem * -gk20a_instobj_acquire(struct nvkm_memory *memory) +gk20a_instobj_acquire_dma(struct nvkm_memory *memory) { struct gk20a_instobj *node = gk20a_instobj(memory); struct gk20a_instmem *imem = node->imem; struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; + + nvkm_ltc_flush(ltc); + + return node->vaddr; +} + +static void __iomem * +gk20a_instobj_acquire_iommu(struct nvkm_memory *memory) +{ + struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory); + struct gk20a_instmem *imem = node->base.imem; + struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; const u64 size = nvkm_memory_size(memory); unsigned long flags; @@ -201,19 +190,21 @@ gk20a_instobj_acquire(struct nvkm_memory *memory) spin_lock_irqsave(&imem->lock, flags); - if (node->vaddr) { - /* remove us from the LRU list since we cannot be unmapped */ - list_del(&node->vaddr_node); - + if (node->base.vaddr) { + if (!node->use_cpt) { + /* remove from LRU list since mapping in use again */ + list_del(&node->vaddr_node); + } goto out; } /* try to free some address space if we reached the limit */ gk20a_instmem_vaddr_gc(imem, size); - node->vaddr = imem->cpu_map(memory); - - if (!node->vaddr) { + /* map the pages */ + node->base.vaddr = vmap(node->pages, size >> PAGE_SHIFT, VM_MAP, + pgprot_writecombine(PAGE_KERNEL)); + if (!node->base.vaddr) { nvkm_error(&imem->base.subdev, "cannot map instobj - " "this is not going to end well...\n"); goto out; @@ -224,24 +215,41 @@ gk20a_instobj_acquire(struct nvkm_memory *memory) imem->vaddr_use, imem->vaddr_max); out: + node->use_cpt++; spin_unlock_irqrestore(&imem->lock, flags); - return node->vaddr; + return node->base.vaddr; } static void -gk20a_instobj_release(struct nvkm_memory *memory) +gk20a_instobj_release_dma(struct nvkm_memory *memory) { struct gk20a_instobj *node = gk20a_instobj(memory); struct gk20a_instmem *imem = node->imem; struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; + + nvkm_ltc_invalidate(ltc); +} + +static void +gk20a_instobj_release_iommu(struct nvkm_memory *memory) +{ + struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory); + struct gk20a_instmem *imem = node->base.imem; + struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; unsigned long flags; spin_lock_irqsave(&imem->lock, flags); - /* add ourselves to the LRU list so our CPU mapping can be freed */ - list_add_tail(&node->vaddr_node, &imem->vaddr_lru); + /* we should at least have one user to release... */ + if (WARN_ON(node->use_cpt == 0)) + goto out; + + /* add unused objs to the LRU list to recycle their mapping */ + if (--node->use_cpt == 0) + list_add_tail(&node->vaddr_node, &imem->vaddr_lru); +out: spin_unlock_irqrestore(&imem->lock, flags); wmb(); @@ -272,37 +280,6 @@ gk20a_instobj_map(struct nvkm_memory *memory, struct nvkm_vma *vma, u64 offset) nvkm_vm_map_at(vma, offset, &node->mem); } -/* - * Clear the CPU mapping of an instobj if it exists - */ -static void -gk20a_instobj_dtor(struct gk20a_instobj *node) -{ - struct gk20a_instmem *imem = node->imem; - struct gk20a_instobj *obj; - unsigned long flags; - - spin_lock_irqsave(&imem->lock, flags); - - if (!node->vaddr) - goto out; - - list_for_each_entry(obj, &imem->vaddr_lru, vaddr_node) { - if (obj == node) { - list_del(&obj->vaddr_node); - break; - } - } - vunmap(node->vaddr); - node->vaddr = NULL; - imem->vaddr_use -= nvkm_memory_size(&node->memory); - nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", - imem->vaddr_use, imem->vaddr_max); - -out: - spin_unlock_irqrestore(&imem->lock, flags); -} - static void * gk20a_instobj_dtor_dma(struct nvkm_memory *memory) { @@ -310,12 +287,10 @@ gk20a_instobj_dtor_dma(struct nvkm_memory *memory) struct gk20a_instmem *imem = node->base.imem; struct device *dev = imem->base.subdev.device->dev; - gk20a_instobj_dtor(&node->base); - - if (unlikely(!node->cpuaddr)) + if (unlikely(!node->base.vaddr)) goto out; - dma_free_attrs(dev, node->base.mem.size << PAGE_SHIFT, node->cpuaddr, + dma_free_attrs(dev, node->base.mem.size << PAGE_SHIFT, node->base.vaddr, node->handle, &imem->attrs); out: @@ -329,13 +304,20 @@ gk20a_instobj_dtor_iommu(struct nvkm_memory *memory) struct gk20a_instmem *imem = node->base.imem; struct device *dev = imem->base.subdev.device->dev; struct nvkm_mm_node *r; + unsigned long flags; int i; - gk20a_instobj_dtor(&node->base); - if (unlikely(list_empty(&node->base.mem.regions))) goto out; + spin_lock_irqsave(&imem->lock, flags); + + /* vaddr has already been recycled */ + if (node->base.vaddr) + gk20a_instobj_iommu_recycle_vaddr(node); + + spin_unlock_irqrestore(&imem->lock, flags); + r = list_first_entry(&node->base.mem.regions, struct nvkm_mm_node, rl_entry); @@ -366,8 +348,8 @@ gk20a_instobj_func_dma = { .target = gk20a_instobj_target, .addr = gk20a_instobj_addr, .size = gk20a_instobj_size, - .acquire = gk20a_instobj_acquire, - .release = gk20a_instobj_release, + .acquire = gk20a_instobj_acquire_dma, + .release = gk20a_instobj_release_dma, .rd32 = gk20a_instobj_rd32, .wr32 = gk20a_instobj_wr32, .map = gk20a_instobj_map, @@ -379,8 +361,8 @@ gk20a_instobj_func_iommu = { .target = gk20a_instobj_target, .addr = gk20a_instobj_addr, .size = gk20a_instobj_size, - .acquire = gk20a_instobj_acquire, - .release = gk20a_instobj_release, + .acquire = gk20a_instobj_acquire_iommu, + .release = gk20a_instobj_release_iommu, .rd32 = gk20a_instobj_rd32, .wr32 = gk20a_instobj_wr32, .map = gk20a_instobj_map, @@ -400,10 +382,10 @@ gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align, nvkm_memory_ctor(&gk20a_instobj_func_dma, &node->base.memory); - node->cpuaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, - &node->handle, GFP_KERNEL, - &imem->attrs); - if (!node->cpuaddr) { + node->base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, + &node->handle, GFP_KERNEL, + &imem->attrs); + if (!node->base.vaddr) { nvkm_error(subdev, "cannot allocate DMA memory\n"); return -ENOMEM; } @@ -609,18 +591,14 @@ gk20a_instmem_new(struct nvkm_device *device, int index, imem->mm = &tdev->iommu.mm; imem->domain = tdev->iommu.domain; imem->iommu_pgshift = tdev->iommu.pgshift; - imem->cpu_map = gk20a_instobj_cpu_map_iommu; imem->iommu_bit = tdev->func->iommu_bit; nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { init_dma_attrs(&imem->attrs); - /* We will access the memory through our own mapping */ dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); - dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &imem->attrs); - imem->cpu_map = gk20a_instobj_cpu_map_dma; nvkm_info(&imem->base.subdev, "using DMA API\n"); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild index e5df3d865f0c..f8108df3cb38 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild @@ -2,3 +2,4 @@ nvkm-y += nvkm/subdev/ltc/base.o nvkm-y += nvkm/subdev/ltc/gf100.o nvkm-y += nvkm/subdev/ltc/gk104.o nvkm-y += nvkm/subdev/ltc/gm107.o +nvkm-y += nvkm/subdev/ltc/gm204.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c index 3043bbfd7384..2af1f9e100fc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -26,16 +26,16 @@ #include <subdev/fb.h> #include <subdev/timer.h> -static void +void gm107_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit) { struct nvkm_device *device = ltc->subdev.device; nvkm_wr32(device, 0x17e270, start); nvkm_wr32(device, 0x17e274, limit); - nvkm_wr32(device, 0x17e26c, 0x00000004); + nvkm_mask(device, 0x17e26c, 0x00000000, 0x00000004); } -static void +void gm107_ltc_cbc_wait(struct nvkm_ltc *ltc) { struct nvkm_device *device = ltc->subdev.device; @@ -51,7 +51,7 @@ gm107_ltc_cbc_wait(struct nvkm_ltc *ltc) } } -static void +void gm107_ltc_zbc_clear_color(struct nvkm_ltc *ltc, int i, const u32 color[4]) { struct nvkm_device *device = ltc->subdev.device; @@ -62,7 +62,7 @@ gm107_ltc_zbc_clear_color(struct nvkm_ltc *ltc, int i, const u32 color[4]) nvkm_wr32(device, 0x17e348, color[3]); } -static void +void gm107_ltc_zbc_clear_depth(struct nvkm_ltc *ltc, int i, const u32 depth) { struct nvkm_device *device = ltc->subdev.device; @@ -84,7 +84,7 @@ gm107_ltc_lts_isr(struct nvkm_ltc *ltc, int c, int s) } } -static void +void gm107_ltc_intr(struct nvkm_ltc *ltc) { struct nvkm_device *device = ltc->subdev.device; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm204.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm204.c new file mode 100644 index 000000000000..5ad6fb9d022d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm204.c @@ -0,0 +1,63 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ +#include "priv.h" + +#include <subdev/fb.h> +#include <subdev/timer.h> + +static int +gm204_ltc_oneinit(struct nvkm_ltc *ltc) +{ + struct nvkm_device *device = ltc->subdev.device; + + ltc->ltc_nr = nvkm_rd32(device, 0x12006c); + ltc->lts_nr = nvkm_rd32(device, 0x17e280) >> 28; + + return gf100_ltc_oneinit_tag_ram(ltc); +} +static void +gm204_ltc_init(struct nvkm_ltc *ltc) +{ + nvkm_wr32(ltc->subdev.device, 0x17e278, ltc->tag_base); +} + +static const struct nvkm_ltc_func +gm204_ltc = { + .oneinit = gm204_ltc_oneinit, + .init = gm204_ltc_init, + .intr = gm107_ltc_intr, /*XXX: not validated */ + .cbc_clear = gm107_ltc_cbc_clear, + .cbc_wait = gm107_ltc_cbc_wait, + .zbc = 16, + .zbc_clear_color = gm107_ltc_zbc_clear_color, + .zbc_clear_depth = gm107_ltc_zbc_clear_depth, + .invalidate = gf100_ltc_invalidate, + .flush = gf100_ltc_flush, +}; + +int +gm204_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +{ + return nvkm_ltc_new_(&gm204_ltc, device, index, pltc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h index 4e3755b82769..6d81c695ed0d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -31,4 +31,10 @@ void gf100_ltc_zbc_clear_color(struct nvkm_ltc *, int, const u32[4]); void gf100_ltc_zbc_clear_depth(struct nvkm_ltc *, int, const u32); void gf100_ltc_invalidate(struct nvkm_ltc *); void gf100_ltc_flush(struct nvkm_ltc *); + +void gm107_ltc_intr(struct nvkm_ltc *); +void gm107_ltc_cbc_clear(struct nvkm_ltc *, u32, u32); +void gm107_ltc_cbc_wait(struct nvkm_ltc *); +void gm107_ltc_zbc_clear_color(struct nvkm_ltc *, int, const u32[4]); +void gm107_ltc_zbc_clear_depth(struct nvkm_ltc *, int, const u32); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild index 4476ef75acd6..3c2519fdeb81 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild @@ -1,5 +1,6 @@ nvkm-y += nvkm/subdev/pci/agp.o nvkm-y += nvkm/subdev/pci/base.o +nvkm-y += nvkm/subdev/pci/pcie.o nvkm-y += nvkm/subdev/pci/nv04.o nvkm-y += nvkm/subdev/pci/nv40.o nvkm-y += nvkm/subdev/pci/nv46.o @@ -7,3 +8,5 @@ nvkm-y += nvkm/subdev/pci/nv4c.o nvkm-y += nvkm/subdev/pci/g84.o nvkm-y += nvkm/subdev/pci/g94.o nvkm-y += nvkm/subdev/pci/gf100.o +nvkm-y += nvkm/subdev/pci/gf106.o +nvkm-y += nvkm/subdev/pci/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c index d671dcfaff3c..65057c8310a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c @@ -107,6 +107,15 @@ nvkm_pci_preinit(struct nvkm_subdev *subdev) } static int +nvkm_pci_oneinit(struct nvkm_subdev *subdev) +{ + struct nvkm_pci *pci = nvkm_pci(subdev); + if (pci_is_pcie(pci->pdev)) + return nvkm_pcie_oneinit(pci); + return 0; +} + +static int nvkm_pci_init(struct nvkm_subdev *subdev) { struct nvkm_pci *pci = nvkm_pci(subdev); @@ -117,6 +126,8 @@ nvkm_pci_init(struct nvkm_subdev *subdev) ret = nvkm_agp_init(pci); if (ret) return ret; + } else if (pci_is_pcie(pci->pdev)) { + nvkm_pcie_init(pci); } if (pci->func->init) @@ -143,6 +154,7 @@ nvkm_pci_dtor(struct nvkm_subdev *subdev) static const struct nvkm_subdev_func nvkm_pci_func = { .dtor = nvkm_pci_dtor, + .oneinit = nvkm_pci_oneinit, .preinit = nvkm_pci_preinit, .init = nvkm_pci_init, .fini = nvkm_pci_fini, @@ -160,6 +172,8 @@ nvkm_pci_new_(const struct nvkm_pci_func *func, struct nvkm_device *device, pci->func = func; pci->pdev = device->func->pci(device)->pdev; pci->irq = -1; + pci->pcie.speed = -1; + pci->pcie.width = -1; if (device->type == NVKM_DEVICE_AGP) nvkm_agp_ctor(pci); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c index 3faa6bfb895b..62438d892f42 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c @@ -25,6 +25,80 @@ #include <core/pci.h> +static int +g84_pcie_version_supported(struct nvkm_pci *pci) +{ + /* g84 and g86 report wrong information about what they support */ + return 1; +} + +int +g84_pcie_version(struct nvkm_pci *pci) +{ + struct nvkm_device *device = pci->subdev.device; + return (nvkm_rd32(device, 0x00154c) & 0x1) + 1; +} + +void +g84_pcie_set_version(struct nvkm_pci *pci, u8 ver) +{ + struct nvkm_device *device = pci->subdev.device; + nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0)); +} + +static void +g84_pcie_set_cap_speed(struct nvkm_pci *pci, bool full_speed) +{ + struct nvkm_device *device = pci->subdev.device; + nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0); +} + +enum nvkm_pcie_speed +g84_pcie_cur_speed(struct nvkm_pci *pci) +{ + u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000; + switch (reg_v) { + case 0x30000: + return NVKM_PCIE_SPEED_8_0; + case 0x20000: + return NVKM_PCIE_SPEED_5_0; + case 0x10000: + default: + return NVKM_PCIE_SPEED_2_5; + } +} + +enum nvkm_pcie_speed +g84_pcie_max_speed(struct nvkm_pci *pci) +{ + u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300; + if (reg_v == 0x2200) + return NVKM_PCIE_SPEED_5_0; + return NVKM_PCIE_SPEED_2_5; +} + +void +g84_pcie_set_link_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed) +{ + u32 mask_value; + + if (speed == NVKM_PCIE_SPEED_5_0) + mask_value = 0x20; + else + mask_value = 0x10; + + nvkm_pci_mask(pci, 0x460, 0x30, mask_value); + nvkm_pci_mask(pci, 0x460, 0x1, 0x1); +} + +int +g84_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width) +{ + g84_pcie_set_cap_speed(pci, speed == NVKM_PCIE_SPEED_5_0); + g84_pcie_set_link_speed(pci, speed); + return 0; +} + void g84_pci_init(struct nvkm_pci *pci) { @@ -48,6 +122,14 @@ g84_pci_init(struct nvkm_pci *pci) nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000); } +int +g84_pcie_init(struct nvkm_pci *pci) +{ + bool full_speed = g84_pcie_cur_speed(pci) == NVKM_PCIE_SPEED_5_0; + g84_pcie_set_cap_speed(pci, full_speed); + return 0; +} + static const struct nvkm_pci_func g84_pci_func = { .init = g84_pci_init, @@ -55,6 +137,16 @@ g84_pci_func = { .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, .msi_rearm = nv46_pci_msi_rearm, + + .pcie.init = g84_pcie_init, + .pcie.set_link = g84_pcie_set_link, + + .pcie.max_speed = g84_pcie_max_speed, + .pcie.cur_speed = g84_pcie_cur_speed, + + .pcie.set_version = g84_pcie_set_version, + .pcie.version = g84_pcie_version, + .pcie.version_supported = g84_pcie_version_supported, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c index cd311ee311cc..43444123bc04 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c @@ -23,6 +23,14 @@ */ #include "priv.h" +int +g94_pcie_version_supported(struct nvkm_pci *pci) +{ + if ((nvkm_pci_rd32(pci, 0x460) & 0x200) == 0x200) + return 2; + return 1; +} + static const struct nvkm_pci_func g94_pci_func = { .init = g84_pci_init, @@ -30,6 +38,16 @@ g94_pci_func = { .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, .msi_rearm = nv40_pci_msi_rearm, + + .pcie.init = g84_pcie_init, + .pcie.set_link = g84_pcie_set_link, + + .pcie.max_speed = g84_pcie_max_speed, + .pcie.cur_speed = g84_pcie_cur_speed, + + .pcie.set_version = g84_pcie_set_version, + .pcie.version = g84_pcie_version, + .pcie.version_supported = g94_pcie_version_supported, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c index 25e1ae70867f..e30ea676baf6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c @@ -29,6 +29,53 @@ gf100_pci_msi_rearm(struct nvkm_pci *pci) nvkm_pci_wr08(pci, 0x0704, 0xff); } +void +gf100_pcie_set_version(struct nvkm_pci *pci, u8 ver) +{ + struct nvkm_device *device = pci->subdev.device; + nvkm_mask(device, 0x02241c, 0x1, ver > 1 ? 1 : 0); +} + +int +gf100_pcie_version(struct nvkm_pci *pci) +{ + struct nvkm_device *device = pci->subdev.device; + return (nvkm_rd32(device, 0x02241c) & 0x1) + 1; +} + +void +gf100_pcie_set_cap_speed(struct nvkm_pci *pci, bool full_speed) +{ + struct nvkm_device *device = pci->subdev.device; + nvkm_mask(device, 0x02241c, 0x80, full_speed ? 0x80 : 0x0); +} + +int +gf100_pcie_cap_speed(struct nvkm_pci *pci) +{ + struct nvkm_device *device = pci->subdev.device; + u8 punits_pci_cap_speed = nvkm_rd32(device, 0x02241c) & 0x80; + if (punits_pci_cap_speed == 0x80) + return 1; + return 0; +} + +int +gf100_pcie_init(struct nvkm_pci *pci) +{ + bool full_speed = g84_pcie_cur_speed(pci) == NVKM_PCIE_SPEED_5_0; + gf100_pcie_set_cap_speed(pci, full_speed); + return 0; +} + +int +gf100_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width) +{ + gf100_pcie_set_cap_speed(pci, speed == NVKM_PCIE_SPEED_5_0); + g84_pcie_set_link_speed(pci, speed); + return 0; +} + static const struct nvkm_pci_func gf100_pci_func = { .init = g84_pci_init, @@ -36,6 +83,16 @@ gf100_pci_func = { .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, .msi_rearm = gf100_pci_msi_rearm, + + .pcie.init = gf100_pcie_init, + .pcie.set_link = gf100_pcie_set_link, + + .pcie.max_speed = g84_pcie_max_speed, + .pcie.cur_speed = g84_pcie_cur_speed, + + .pcie.set_version = gf100_pcie_set_version, + .pcie.version = gf100_pcie_version, + .pcie.version_supported = g94_pcie_version_supported, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c new file mode 100644 index 000000000000..c3b798c5c6dd --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c @@ -0,0 +1,49 @@ +/* + * Copyright 2015 Karol Herbst <nouveau@karolherbst.de> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Karol Herbst <nouveau@karolherbst.de> + */ +#include "priv.h" + +static const struct nvkm_pci_func +gf106_pci_func = { + .init = g84_pci_init, + .rd32 = nv40_pci_rd32, + .wr08 = nv40_pci_wr08, + .wr32 = nv40_pci_wr32, + .msi_rearm = nv40_pci_msi_rearm, + + .pcie.init = gf100_pcie_init, + .pcie.set_link = gf100_pcie_set_link, + + .pcie.max_speed = g84_pcie_max_speed, + .pcie.cur_speed = g84_pcie_cur_speed, + + .pcie.set_version = gf100_pcie_set_version, + .pcie.version = gf100_pcie_version, + .pcie.version_supported = g94_pcie_version_supported, +}; + +int +gf106_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +{ + return nvkm_pci_new_(&gf106_pci_func, device, index, ppci); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c new file mode 100644 index 000000000000..e68030507d88 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c @@ -0,0 +1,228 @@ +/* + * Copyright 2015 Karol Herbst <nouveau@karolherbst.de> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Karol Herbst <nouveau@karolherbst.de> + */ +#include "priv.h" + +static int +gk104_pcie_version_supported(struct nvkm_pci *pci) +{ + return (nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x4) == 0x4 ? 2 : 1; +} + +static void +gk104_pcie_set_cap_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed) +{ + struct nvkm_device *device = pci->subdev.device; + + switch (speed) { + case NVKM_PCIE_SPEED_2_5: + gf100_pcie_set_cap_speed(pci, false); + nvkm_mask(device, 0x8c1c0, 0x30000, 0x10000); + break; + case NVKM_PCIE_SPEED_5_0: + gf100_pcie_set_cap_speed(pci, true); + nvkm_mask(device, 0x8c1c0, 0x30000, 0x20000); + break; + case NVKM_PCIE_SPEED_8_0: + gf100_pcie_set_cap_speed(pci, true); + nvkm_mask(device, 0x8c1c0, 0x30000, 0x30000); + break; + } +} + +static enum nvkm_pcie_speed +gk104_pcie_cap_speed(struct nvkm_pci *pci) +{ + int speed = gf100_pcie_cap_speed(pci); + + if (speed == 0) + return NVKM_PCIE_SPEED_2_5; + + if (speed >= 1) { + int speed2 = nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x30000; + switch (speed2) { + case 0x00000: + case 0x10000: + return NVKM_PCIE_SPEED_2_5; + case 0x20000: + return NVKM_PCIE_SPEED_5_0; + case 0x30000: + return NVKM_PCIE_SPEED_8_0; + } + } + + return -EINVAL; +} + +static void +gk104_pcie_set_lnkctl_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed) +{ + u8 reg_v = 0; + switch (speed) { + case NVKM_PCIE_SPEED_2_5: + reg_v = 1; + break; + case NVKM_PCIE_SPEED_5_0: + reg_v = 2; + break; + case NVKM_PCIE_SPEED_8_0: + reg_v = 3; + break; + } + nvkm_pci_mask(pci, 0xa8, 0x3, reg_v); +} + +static enum nvkm_pcie_speed +gk104_pcie_lnkctl_speed(struct nvkm_pci *pci) +{ + u8 reg_v = nvkm_pci_rd32(pci, 0xa8) & 0x3; + switch (reg_v) { + case 0: + case 1: + return NVKM_PCIE_SPEED_2_5; + case 2: + return NVKM_PCIE_SPEED_5_0; + case 3: + return NVKM_PCIE_SPEED_8_0; + } + return -1; +} + +static enum nvkm_pcie_speed +gk104_pcie_max_speed(struct nvkm_pci *pci) +{ + u32 max_speed = nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x300000; + switch (max_speed) { + case 0x000000: + return NVKM_PCIE_SPEED_8_0; + case 0x100000: + return NVKM_PCIE_SPEED_5_0; + case 0x200000: + return NVKM_PCIE_SPEED_2_5; + } + return NVKM_PCIE_SPEED_2_5; +} + +static void +gk104_pcie_set_link_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed) +{ + struct nvkm_device *device = pci->subdev.device; + u32 mask_value; + + switch (speed) { + case NVKM_PCIE_SPEED_8_0: + mask_value = 0x00000; + break; + case NVKM_PCIE_SPEED_5_0: + mask_value = 0x40000; + break; + case NVKM_PCIE_SPEED_2_5: + default: + mask_value = 0x80000; + break; + } + + nvkm_mask(device, 0x8c040, 0xc0000, mask_value); + nvkm_mask(device, 0x8c040, 0x1, 0x1); +} + +static int +gk104_pcie_init(struct nvkm_pci * pci) +{ + enum nvkm_pcie_speed lnkctl_speed, max_speed, cap_speed; + struct nvkm_subdev *subdev = &pci->subdev; + + if (gf100_pcie_version(pci) < 2) + return 0; + + lnkctl_speed = gk104_pcie_lnkctl_speed(pci); + max_speed = gk104_pcie_max_speed(pci); + cap_speed = gk104_pcie_cap_speed(pci); + + if (cap_speed != max_speed) { + nvkm_trace(subdev, "adjusting cap to max speed\n"); + gk104_pcie_set_cap_speed(pci, max_speed); + cap_speed = gk104_pcie_cap_speed(pci); + if (cap_speed != max_speed) + nvkm_warn(subdev, "failed to adjust cap speed\n"); + } + + if (lnkctl_speed != max_speed) { + nvkm_debug(subdev, "adjusting lnkctl to max speed\n"); + gk104_pcie_set_lnkctl_speed(pci, max_speed); + lnkctl_speed = gk104_pcie_lnkctl_speed(pci); + if (lnkctl_speed != max_speed) + nvkm_error(subdev, "failed to adjust lnkctl speed\n"); + } + + return 0; +} + +static int +gk104_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width) +{ + struct nvkm_subdev *subdev = &pci->subdev; + enum nvkm_pcie_speed lnk_ctl_speed = gk104_pcie_lnkctl_speed(pci); + enum nvkm_pcie_speed lnk_cap_speed = gk104_pcie_cap_speed(pci); + + if (speed > lnk_cap_speed) { + speed = lnk_cap_speed; + nvkm_warn(subdev, "dropping requested speed due too low cap" + " speed\n"); + } + + if (speed > lnk_ctl_speed) { + speed = lnk_ctl_speed; + nvkm_warn(subdev, "dropping requested speed due too low" + " lnkctl speed\n"); + } + + gk104_pcie_set_link_speed(pci, speed); + return 0; +} + + +static const struct nvkm_pci_func +gk104_pci_func = { + .init = g84_pci_init, + .rd32 = nv40_pci_rd32, + .wr08 = nv40_pci_wr08, + .wr32 = nv40_pci_wr32, + .msi_rearm = nv40_pci_msi_rearm, + + .pcie.init = gk104_pcie_init, + .pcie.set_link = gk104_pcie_set_link, + + .pcie.max_speed = gk104_pcie_max_speed, + .pcie.cur_speed = g84_pcie_cur_speed, + + .pcie.set_version = gf100_pcie_set_version, + .pcie.version = gf100_pcie_version, + .pcie.version_supported = gk104_pcie_version_supported, +}; + +int +gk104_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +{ + return nvkm_pci_new_(&gk104_pci_func, device, index, ppci); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c new file mode 100644 index 000000000000..b32954f5311e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c @@ -0,0 +1,165 @@ +/* + * Copyright 2015 Karol Herbst <nouveau@karolherbst.de> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Karol Herbst <git@karolherbst.de> + */ +#include "priv.h" + +static char *nvkm_pcie_speeds[] = { + "2.5GT/s", + "5.0GT/s", + "8.0GT/s", +}; + +static enum nvkm_pcie_speed +nvkm_pcie_speed(enum pci_bus_speed speed) +{ + switch (speed) { + case PCIE_SPEED_2_5GT: + return NVKM_PCIE_SPEED_2_5; + case PCIE_SPEED_5_0GT: + return NVKM_PCIE_SPEED_5_0; + case PCIE_SPEED_8_0GT: + return NVKM_PCIE_SPEED_8_0; + default: + /* XXX 0x16 is 8_0, assume 0x17 will be 16_0 for now */ + if (speed == 0x17) + return NVKM_PCIE_SPEED_8_0; + return -1; + } +} + +static int +nvkm_pcie_get_version(struct nvkm_pci *pci) +{ + if (!pci->func->pcie.version) + return -ENOSYS; + + return pci->func->pcie.version(pci); +} + +static int +nvkm_pcie_get_max_version(struct nvkm_pci *pci) +{ + if (!pci->func->pcie.version_supported) + return -ENOSYS; + + return pci->func->pcie.version_supported(pci); +} + +static int +nvkm_pcie_set_version(struct nvkm_pci *pci, int version) +{ + if (!pci->func->pcie.set_version) + return -ENOSYS; + + nvkm_trace(&pci->subdev, "set to version %i\n", version); + pci->func->pcie.set_version(pci, version); + return nvkm_pcie_get_version(pci); +} + +int +nvkm_pcie_oneinit(struct nvkm_pci *pci) +{ + if (pci->func->pcie.max_speed) + nvkm_debug(&pci->subdev, "pcie max speed: %s\n", + nvkm_pcie_speeds[pci->func->pcie.max_speed(pci)]); + return 0; +} + +int +nvkm_pcie_init(struct nvkm_pci *pci) +{ + struct nvkm_subdev *subdev = &pci->subdev; + int ret; + + /* raise pcie version first */ + ret = nvkm_pcie_get_version(pci); + if (ret > 0) { + int max_version = nvkm_pcie_get_max_version(pci); + if (max_version > 0 && max_version > ret) + ret = nvkm_pcie_set_version(pci, max_version); + + if (ret < max_version) + nvkm_error(subdev, "couldn't raise version: %i\n", ret); + } + + if (pci->func->pcie.init) + pci->func->pcie.init(pci); + + if (pci->pcie.speed != -1) + nvkm_pcie_set_link(pci, pci->pcie.speed, pci->pcie.width); + + return 0; +} + +int +nvkm_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width) +{ + struct nvkm_subdev *subdev = &pci->subdev; + enum nvkm_pcie_speed cur_speed, max_speed; + struct pci_bus *pbus; + int ret; + + if (pci || !pci_is_pcie(pci->pdev)) + return 0; + pbus = pci->pdev->bus; + + if (!pci->func->pcie.set_link) + return -ENOSYS; + + nvkm_trace(subdev, "requested %s\n", nvkm_pcie_speeds[speed]); + + if (pci->func->pcie.version(pci) < 2) { + nvkm_error(subdev, "setting link failed due to low version\n"); + return -ENODEV; + } + + cur_speed = pci->func->pcie.cur_speed(pci); + max_speed = min(nvkm_pcie_speed(pbus->max_bus_speed), + pci->func->pcie.max_speed(pci)); + + nvkm_trace(subdev, "current speed: %s\n", nvkm_pcie_speeds[cur_speed]); + + if (speed > max_speed) { + nvkm_debug(subdev, "%s not supported by bus or card, dropping" + "requested speed to %s", nvkm_pcie_speeds[speed], + nvkm_pcie_speeds[max_speed]); + speed = max_speed; + } + + pci->pcie.speed = speed; + pci->pcie.width = width; + + if (speed == cur_speed) { + nvkm_debug(subdev, "requested matches current speed\n"); + return speed; + } + + nvkm_debug(subdev, "set link to %s x%i\n", + nvkm_pcie_speeds[speed], width); + + ret = pci->func->pcie.set_link(pci, speed, width); + if (ret < 0) + nvkm_error(subdev, "setting link failed: %i\n", ret); + + return ret; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h index cf46d38d0b0a..23de3180aae5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h @@ -12,6 +12,18 @@ struct nvkm_pci_func { void (*wr08)(struct nvkm_pci *, u16 addr, u8 data); void (*wr32)(struct nvkm_pci *, u16 addr, u32 data); void (*msi_rearm)(struct nvkm_pci *); + + struct { + int (*init)(struct nvkm_pci *); + int (*set_link)(struct nvkm_pci *, enum nvkm_pcie_speed, u8); + + enum nvkm_pcie_speed (*max_speed)(struct nvkm_pci *); + enum nvkm_pcie_speed (*cur_speed)(struct nvkm_pci *); + + void (*set_version)(struct nvkm_pci *, u8); + int (*version)(struct nvkm_pci *); + int (*version_supported)(struct nvkm_pci *); + } pcie; }; u32 nv40_pci_rd32(struct nvkm_pci *, u16); @@ -22,4 +34,25 @@ void nv40_pci_msi_rearm(struct nvkm_pci *); void nv46_pci_msi_rearm(struct nvkm_pci *); void g84_pci_init(struct nvkm_pci *pci); + +/* pcie functions */ +void g84_pcie_set_version(struct nvkm_pci *, u8); +int g84_pcie_version(struct nvkm_pci *); +void g84_pcie_set_link_speed(struct nvkm_pci *, enum nvkm_pcie_speed); +enum nvkm_pcie_speed g84_pcie_cur_speed(struct nvkm_pci *); +enum nvkm_pcie_speed g84_pcie_max_speed(struct nvkm_pci *); +int g84_pcie_init(struct nvkm_pci *); +int g84_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8); + +int g94_pcie_version_supported(struct nvkm_pci *); + +void gf100_pcie_set_version(struct nvkm_pci *, u8); +int gf100_pcie_version(struct nvkm_pci *); +void gf100_pcie_set_cap_speed(struct nvkm_pci *, bool); +int gf100_pcie_cap_speed(struct nvkm_pci *); +int gf100_pcie_init(struct nvkm_pci *); +int gf100_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8); + +int nvkm_pcie_oneinit(struct nvkm_pci *); +int nvkm_pcie_init(struct nvkm_pci *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h index 302557c52d03..770294457274 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h @@ -24,8 +24,8 @@ uint32_t gf100_pmu_data[] = { 0x00000000, /* 0x0058: proc_list_head */ 0x54534f48, - 0x00000512, - 0x000004af, + 0x00000507, + 0x000004a4, 0x00000000, 0x00000000, 0x00000000, @@ -46,8 +46,8 @@ uint32_t gf100_pmu_data[] = { 0x00000000, 0x00000000, 0x584d454d, - 0x0000075e, - 0x00000750, + 0x00000753, + 0x00000745, 0x00000000, 0x00000000, 0x00000000, @@ -68,8 +68,8 @@ uint32_t gf100_pmu_data[] = { 0x00000000, 0x00000000, 0x46524550, - 0x00000762, - 0x00000760, + 0x00000757, + 0x00000755, 0x00000000, 0x00000000, 0x00000000, @@ -90,8 +90,8 @@ uint32_t gf100_pmu_data[] = { 0x00000000, 0x00000000, 0x5f433249, - 0x00000b92, - 0x00000a35, + 0x00000b87, + 0x00000a2a, 0x00000000, 0x00000000, 0x00000000, @@ -112,8 +112,8 @@ uint32_t gf100_pmu_data[] = { 0x00000000, 0x00000000, 0x54534554, - 0x00000bbb, - 0x00000b94, + 0x00000bb0, + 0x00000b89, 0x00000000, 0x00000000, 0x00000000, @@ -134,8 +134,8 @@ uint32_t gf100_pmu_data[] = { 0x00000000, 0x00000000, 0x454c4449, - 0x00000bc7, - 0x00000bc5, + 0x00000bbc, + 0x00000bba, 0x00000000, 0x00000000, 0x00000000, @@ -229,26 +229,26 @@ uint32_t gf100_pmu_data[] = { /* 0x0370: memx_func_head */ 0x00000001, 0x00000000, - 0x00000551, + 0x00000546, /* 0x037c: memx_func_next */ 0x00000002, 0x00000000, - 0x000005db, + 0x000005d0, 0x00000003, 0x00000002, - 0x000006a5, + 0x0000069a, 0x00040004, 0x00000000, - 0x000006c1, + 0x000006b6, 0x00010005, 0x00000000, - 0x000006de, + 0x000006d3, 0x00010006, 0x00000000, - 0x00000663, + 0x00000658, 0x00000007, 0x00000000, - 0x000006e9, + 0x000006de, /* 0x03c4: memx_func_tail */ /* 0x03c4: memx_ts_start */ 0x00000000, @@ -917,7 +917,7 @@ uint32_t gf100_pmu_data[] = { }; uint32_t gf100_pmu_code[] = { - 0x039e0ef5, + 0x03930ef5, /* 0x0004: rd32 */ 0x07a007f1, 0xd00604b6, @@ -987,7 +987,7 @@ uint32_t gf100_pmu_code[] = { 0xbb9a0a98, 0x1cf4029a, 0x01d7f00f, - 0x02dd21f5, + 0x02d221f5, 0x0ef494bd, /* 0x00f9: intr_watchdog_next_time */ 0x9b0a9815, @@ -1039,7 +1039,7 @@ uint32_t gf100_pmu_code[] = { 0x48e7f1c0, 0x53e3f14f, 0x00d7f054, - 0x034221f5, + 0x033721f5, 0x07f1c0fc, 0x04b604c0, 0x000cd006, @@ -1048,760 +1048,758 @@ uint32_t gf100_pmu_code[] = { 0x04b60688, 0x0009d006, /* 0x01ca: intr_skip_subintr */ - 0x89c404bd, - 0x070bf420, - 0xffbfa4f1, -/* 0x01d4: intr_skip_pause */ - 0xf44089c4, - 0xa4f1070b, -/* 0x01de: intr_skip_user0 */ - 0x07f0ffbf, - 0x0604b604, - 0xbd0008d0, - 0xfe80fc04, - 0xf0fc0088, - 0xd0fce0fc, - 0xb0fcc0fc, - 0x90fca0fc, - 0x00fc80fc, - 0xf80032f4, -/* 0x0205: ticks_from_ns */ - 0xf9c0f901, - 0xcbd7f1b0, - 0x00d3f000, - 0x041321f5, - 0x03e8ccec, - 0xf400b4b0, - 0xeeec120b, - 0xd7f103e8, - 0xd3f000cb, - 0x1321f500, -/* 0x022d: ticks_from_ns_quit */ - 0x02ceb904, - 0xc0fcb0fc, -/* 0x0236: ticks_from_us */ - 0xc0f900f8, + 0x97f104bd, + 0x90bd00e0, + 0xf00489fd, + 0x04b60407, + 0x0008d006, + 0x80fc04bd, + 0xfc0088fe, + 0xfce0fcf0, + 0xfcc0fcd0, + 0xfca0fcb0, + 0xfc80fc90, + 0x0032f400, +/* 0x01fa: ticks_from_ns */ + 0xc0f901f8, 0xd7f1b0f9, 0xd3f000cb, - 0x1321f500, - 0x02ceb904, - 0xf400b4b0, - 0xe4bd050b, -/* 0x0250: ticks_from_us_quit */ - 0xc0fcb0fc, -/* 0x0256: ticks_to_us */ - 0xd7f100f8, - 0xd3f000cb, - 0xecedff00, -/* 0x0262: timer */ - 0x90f900f8, - 0x32f480f9, - 0x03f89810, - 0xf40086b0, - 0x84bd651c, - 0xb63807f0, - 0x08d00604, - 0xf004bd00, - 0x84b63487, - 0x0088cf06, - 0xbb9a0998, - 0xe9bb0298, - 0x03fe8000, - 0xb60887f0, - 0x88cf0684, - 0x0284f000, - 0xf0261bf4, - 0x84b63487, - 0x0088cf06, - 0xf406e0b8, - 0xe8b8090b, - 0x111cf406, -/* 0x02b8: timer_reset */ - 0xb63407f0, - 0x0ed00604, - 0x8004bd00, -/* 0x02c6: timer_enable */ - 0x87f09a0e, - 0x3807f001, + 0x0821f500, + 0xe8ccec04, + 0x00b4b003, + 0xec120bf4, + 0xf103e8ee, + 0xf000cbd7, + 0x21f500d3, +/* 0x0222: ticks_from_ns_quit */ + 0xceb90408, + 0xfcb0fc02, +/* 0x022b: ticks_from_us */ + 0xf900f8c0, + 0xf1b0f9c0, + 0xf000cbd7, + 0x21f500d3, + 0xceb90408, + 0x00b4b002, + 0xbd050bf4, +/* 0x0245: ticks_from_us_quit */ + 0xfcb0fce4, +/* 0x024b: ticks_to_us */ + 0xf100f8c0, + 0xf000cbd7, + 0xedff00d3, +/* 0x0257: timer */ + 0xf900f8ec, + 0xf480f990, + 0xf8981032, + 0x0086b003, + 0xbd651cf4, + 0x3807f084, 0xd00604b6, 0x04bd0008, -/* 0x02d4: timer_done */ - 0xfc1031f4, - 0xf890fc80, -/* 0x02dd: send_proc */ - 0xf980f900, - 0x05e89890, - 0xf004e998, - 0x89b80486, - 0x2a0bf406, - 0x940398c4, - 0x80b60488, - 0x008ebb18, - 0x8000fa98, - 0x8d80008a, - 0x028c8001, - 0xb6038b80, - 0x94f00190, - 0x04e98007, -/* 0x0317: send_done */ - 0xfc0231f4, - 0xf880fc90, -/* 0x031d: find */ - 0xf080f900, - 0x31f45887, -/* 0x0325: find_loop */ - 0x008a9801, - 0xf406aeb8, - 0x80b6100b, - 0x6886b158, - 0xf01bf402, -/* 0x033b: find_done */ - 0xb90132f4, - 0x80fc028e, -/* 0x0342: send */ - 0x21f500f8, - 0x01f4031d, -/* 0x034b: recv */ - 0xf900f897, - 0x9880f990, - 0xe99805e8, - 0x0132f404, - 0xf40689b8, - 0x89c43d0b, - 0x0180b603, - 0x800784f0, - 0xea9805e8, - 0xfef0f902, - 0xf0f9018f, - 0x9402efb9, - 0xe9bb0499, - 0x18e0b600, - 0x9803eb98, - 0xed9802ec, - 0x00ee9801, - 0xf0fca5f9, - 0xf400f8fe, - 0xf0fc0131, -/* 0x0398: recv_done */ - 0x90fc80fc, -/* 0x039e: init */ - 0x17f100f8, - 0x14b60108, - 0x0011cf06, - 0x010911e7, - 0xfe0814b6, - 0x17f10014, - 0x13f000e0, - 0x1c07f000, - 0xd00604b6, - 0x04bd0001, - 0xf0ff17f0, - 0x04b61407, - 0x0001d006, - 0x17f004bd, - 0x0015f102, - 0x1007f008, + 0xb63487f0, + 0x88cf0684, + 0x9a099800, + 0xbb0298bb, + 0xfe8000e9, + 0x0887f003, + 0xcf0684b6, + 0x84f00088, + 0x261bf402, + 0xb63487f0, + 0x88cf0684, + 0x06e0b800, + 0xb8090bf4, + 0x1cf406e8, +/* 0x02ad: timer_reset */ + 0x3407f011, 0xd00604b6, - 0x04bd0001, - 0x011a17f1, - 0xfe0013f0, - 0x31f40010, - 0x0117f010, - 0xb63807f0, + 0x04bd000e, +/* 0x02bb: timer_enable */ + 0xf09a0e80, + 0x07f00187, + 0x0604b638, + 0xbd0008d0, +/* 0x02c9: timer_done */ + 0x1031f404, + 0x90fc80fc, +/* 0x02d2: send_proc */ + 0x80f900f8, + 0xe89890f9, + 0x04e99805, + 0xb80486f0, + 0x0bf40689, + 0x0398c42a, + 0xb6048894, + 0x8ebb1880, + 0x00fa9800, + 0x80008a80, + 0x8c80018d, + 0x038b8002, + 0xf00190b6, + 0xe9800794, + 0x0231f404, +/* 0x030c: send_done */ + 0x80fc90fc, +/* 0x0312: find */ + 0x80f900f8, + 0xf45887f0, +/* 0x031a: find_loop */ + 0x8a980131, + 0x06aeb800, + 0xb6100bf4, + 0x86b15880, + 0x1bf40268, + 0x0132f4f0, +/* 0x0330: find_done */ + 0xfc028eb9, +/* 0x0337: send */ + 0xf500f880, + 0xf4031221, + 0x00f89701, +/* 0x0340: recv */ + 0x80f990f9, + 0x9805e898, + 0x32f404e9, + 0x0689b801, + 0xc43d0bf4, + 0x80b60389, + 0x0784f001, + 0x9805e880, + 0xf0f902ea, + 0xf9018ffe, + 0x02efb9f0, + 0xbb049994, + 0xe0b600e9, + 0x03eb9818, + 0x9802ec98, + 0xee9801ed, + 0xfca5f900, + 0x00f8fef0, + 0xfc0131f4, +/* 0x038d: recv_done */ + 0xfc80fcf0, +/* 0x0393: init */ + 0xf100f890, + 0xb6010817, + 0x11cf0614, + 0x0911e700, + 0x0814b601, + 0xf10014fe, + 0xf000e017, + 0x07f00013, + 0x0604b61c, + 0xbd0001d0, + 0xff17f004, + 0xb61407f0, 0x01d00604, 0xf004bd00, -/* 0x0402: init_proc */ - 0xf19858f7, - 0x0016b001, - 0xf9fa0bf4, - 0x58f0b615, -/* 0x0413: mulu32_32_64 */ - 0xf9f20ef4, - 0xf920f910, - 0x9540f930, - 0xd29510e1, - 0xbdc4bd10, - 0xc0edffb4, - 0xb9301dff, - 0x34f10234, - 0x34b6ffff, - 0x1045b610, - 0xbb00c3bb, - 0xe2ff01b4, - 0x0234b930, - 0xffff34f1, - 0xb61034b6, - 0xc3bb1045, - 0x01b4bb00, - 0xbb3012ff, - 0x40fc00b3, - 0x20fc30fc, - 0x00f810fc, -/* 0x0464: host_send */ - 0x04b017f1, - 0xcf0614b6, - 0x27f10011, - 0x24b604a0, - 0x0022cf06, - 0xf40612b8, - 0x1ec4320b, - 0x04ee9407, - 0x0270e0b7, - 0x9803eb98, - 0xed9802ec, - 0x00ee9801, - 0x034221f5, - 0xc40110b6, - 0x07f10f1e, - 0x04b604b0, - 0x000ed006, - 0x0ef404bd, -/* 0x04ad: host_send_done */ -/* 0x04af: host_recv */ - 0xf100f8ba, - 0xf14e4917, - 0xb8525413, - 0x0bf406e1, -/* 0x04bd: host_recv_wait */ - 0xcc17f1aa, + 0x15f10217, + 0x07f00800, + 0x0604b610, + 0xbd0001d0, + 0x1a17f104, + 0x0013f001, + 0xf40010fe, + 0x17f01031, + 0x3807f001, + 0xd00604b6, + 0x04bd0001, +/* 0x03f7: init_proc */ + 0x9858f7f0, + 0x16b001f1, + 0xfa0bf400, + 0xf0b615f9, + 0xf20ef458, +/* 0x0408: mulu32_32_64 */ + 0x20f910f9, + 0x40f930f9, + 0x9510e195, + 0xc4bd10d2, + 0xedffb4bd, + 0x301dffc0, + 0xf10234b9, + 0xb6ffff34, + 0x45b61034, + 0x00c3bb10, + 0xff01b4bb, + 0x34b930e2, + 0xff34f102, + 0x1034b6ff, + 0xbb1045b6, + 0xb4bb00c3, + 0x3012ff01, + 0xfc00b3bb, + 0xfc30fc40, + 0xf810fc20, +/* 0x0459: host_send */ + 0xb017f100, 0x0614b604, 0xf10011cf, - 0xb604c827, + 0xb604a027, 0x22cf0624, - 0x0816f000, - 0xf40612b8, - 0x23c4e60b, - 0x0434b607, - 0x02f030b7, - 0x80033b80, - 0x3d80023c, - 0x003e8001, - 0xf00120b6, - 0x07f10f24, - 0x04b604c8, - 0x0002d006, - 0x27f004bd, - 0x0007f040, - 0xd00604b6, - 0x04bd0002, -/* 0x0512: host_init */ - 0x17f100f8, + 0x0612b800, + 0xc4320bf4, + 0xee94071e, + 0x70e0b704, + 0x03eb9802, + 0x9802ec98, + 0xee9801ed, + 0x3721f500, + 0x0110b603, + 0xf10f1ec4, + 0xb604b007, + 0x0ed00604, + 0xf404bd00, +/* 0x04a2: host_send_done */ + 0x00f8ba0e, +/* 0x04a4: host_recv */ + 0x4e4917f1, + 0x525413f1, + 0xf406e1b8, +/* 0x04b2: host_recv_wait */ + 0x17f1aa0b, + 0x14b604cc, + 0x0011cf06, + 0x04c827f1, + 0xcf0624b6, + 0x16f00022, + 0x0612b808, + 0xc4e60bf4, + 0x34b60723, + 0xf030b704, + 0x033b8002, + 0x80023c80, + 0x3e80013d, + 0x0120b600, + 0xf10f24f0, + 0xb604c807, + 0x02d00604, + 0xf004bd00, + 0x07f04027, + 0x0604b600, + 0xbd0002d0, +/* 0x0507: host_init */ + 0xf100f804, + 0xb6008017, + 0x15f11014, + 0x07f10270, + 0x04b604d0, + 0x0001d006, + 0x17f104bd, 0x14b60080, - 0x7015f110, - 0xd007f102, + 0xf015f110, + 0xdc07f102, 0x0604b604, 0xbd0001d0, - 0x8017f104, - 0x1014b600, - 0x02f015f1, - 0x04dc07f1, + 0x0117f004, + 0x04c407f1, 0xd00604b6, 0x04bd0001, - 0xf10117f0, - 0xb604c407, - 0x01d00604, - 0xf804bd00, -/* 0x0551: memx_func_enter */ - 0x2067f100, - 0x5d77f116, - 0xff73f1f5, +/* 0x0546: memx_func_enter */ + 0x67f100f8, + 0x77f11620, + 0x73f1f55d, + 0x6eb9ffff, + 0x0421f402, + 0xfd02d8b9, + 0x60f90487, + 0xd0fc80f9, + 0x21f4e0fc, + 0xfe77f13f, + 0xff73f1ff, 0x026eb9ff, 0xb90421f4, 0x87fd02d8, 0xf960f904, 0xfcd0fc80, 0x3f21f4e0, - 0xfffe77f1, - 0xffff73f1, + 0x26f067f1, 0xf4026eb9, 0xd8b90421, 0x0487fd02, 0x80f960f9, 0xe0fcd0fc, - 0xf13f21f4, - 0xb926f067, - 0x21f4026e, - 0x02d8b904, - 0xf90487fd, - 0xfc80f960, - 0xf4e0fcd0, - 0x67f03f21, - 0xe007f104, - 0x0604b607, - 0xbd0006d0, -/* 0x05bd: memx_func_enter_wait */ - 0xc067f104, - 0x0664b607, - 0xf00066cf, - 0x0bf40464, - 0x2c67f0f3, - 0xcf0664b6, - 0x06800066, -/* 0x05db: memx_func_leave */ - 0xf000f8f1, - 0x64b62c67, - 0x0066cf06, - 0xf0f20680, + 0xf03f21f4, 0x07f10467, - 0x04b607e4, + 0x04b607e0, 0x0006d006, -/* 0x05f6: memx_func_leave_wait */ +/* 0x05b2: memx_func_enter_wait */ 0x67f104bd, 0x64b607c0, 0x0066cf06, 0xf40464f0, - 0x67f1f31b, - 0x77f126f0, - 0x73f00001, - 0x026eb900, - 0xb90421f4, - 0x87fd02d8, - 0xf960f905, - 0xfcd0fc80, - 0x3f21f4e0, - 0x162067f1, - 0xf4026eb9, - 0xd8b90421, - 0x0587fd02, - 0x80f960f9, - 0xe0fcd0fc, - 0xf13f21f4, - 0xf00aa277, + 0x67f0f30b, + 0x0664b62c, + 0x800066cf, + 0x00f8f106, +/* 0x05d0: memx_func_leave */ + 0xb62c67f0, + 0x66cf0664, + 0xf2068000, + 0xf10467f0, + 0xb607e407, + 0x06d00604, +/* 0x05eb: memx_func_leave_wait */ + 0xf104bd00, + 0xb607c067, + 0x66cf0664, + 0x0464f000, + 0xf1f31bf4, + 0xf126f067, + 0xf0000177, 0x6eb90073, 0x0421f402, 0xfd02d8b9, 0x60f90587, 0xd0fc80f9, 0x21f4e0fc, -/* 0x0663: memx_func_wait_vblank */ - 0x9800f83f, - 0x66b00016, - 0x130bf400, - 0xf40166b0, - 0x0ef4060b, -/* 0x0675: memx_func_wait_vblank_head1 */ - 0x2077f12e, - 0x070ef400, -/* 0x067c: memx_func_wait_vblank_head0 */ - 0x000877f1, -/* 0x0680: memx_func_wait_vblank_0 */ - 0x07c467f1, - 0xcf0664b6, - 0x67fd0066, - 0xf31bf404, -/* 0x0690: memx_func_wait_vblank_1 */ - 0x07c467f1, - 0xcf0664b6, - 0x67fd0066, - 0xf30bf404, -/* 0x06a0: memx_func_wait_vblank_fini */ - 0xf80410b6, -/* 0x06a5: memx_func_wr32 */ - 0x00169800, - 0xb6011598, - 0x60f90810, - 0xd0fc50f9, - 0x21f4e0fc, - 0x0242b63f, - 0xf8e91bf4, -/* 0x06c1: memx_func_wait */ - 0x2c87f000, - 0xcf0684b6, - 0x1e980088, - 0x011d9800, - 0x98021c98, - 0x10b6031b, - 0xa421f410, -/* 0x06de: memx_func_delay */ - 0x1e9800f8, + 0x2067f13f, + 0x026eb916, + 0xb90421f4, + 0x87fd02d8, + 0xf960f905, + 0xfcd0fc80, + 0x3f21f4e0, + 0x0aa277f1, + 0xb90073f0, + 0x21f4026e, + 0x02d8b904, + 0xf90587fd, + 0xfc80f960, + 0xf4e0fcd0, + 0x00f83f21, +/* 0x0658: memx_func_wait_vblank */ + 0xb0001698, + 0x0bf40066, + 0x0166b013, + 0xf4060bf4, +/* 0x066a: memx_func_wait_vblank_head1 */ + 0x77f12e0e, + 0x0ef40020, +/* 0x0671: memx_func_wait_vblank_head0 */ + 0x0877f107, +/* 0x0675: memx_func_wait_vblank_0 */ + 0xc467f100, + 0x0664b607, + 0xfd0066cf, + 0x1bf40467, +/* 0x0685: memx_func_wait_vblank_1 */ + 0xc467f1f3, + 0x0664b607, + 0xfd0066cf, + 0x0bf40467, +/* 0x0695: memx_func_wait_vblank_fini */ + 0x0410b6f3, +/* 0x069a: memx_func_wr32 */ + 0x169800f8, + 0x01159800, + 0xf90810b6, + 0xfc50f960, + 0xf4e0fcd0, + 0x42b63f21, + 0xe91bf402, +/* 0x06b6: memx_func_wait */ + 0x87f000f8, + 0x0684b62c, + 0x980088cf, + 0x1d98001e, + 0x021c9801, + 0xb6031b98, + 0x21f41010, +/* 0x06d3: memx_func_delay */ + 0x9800f8a4, + 0x10b6001e, + 0x7f21f404, +/* 0x06de: memx_func_train */ + 0x00f800f8, +/* 0x06e0: memx_exec */ + 0xd0f9e0f9, + 0xb902c1b9, +/* 0x06ea: memx_exec_next */ + 0x139802b2, 0x0410b600, + 0x01f034e7, + 0x01e033e7, + 0xf00132b6, + 0x35980c30, + 0xb855f9de, + 0x1ef40612, + 0xf10b98e4, + 0xbbf20c98, + 0xb7f102cb, + 0xb4b607c4, + 0x00bbcf06, + 0xe0fcd0fc, + 0x033721f5, +/* 0x0726: memx_info */ + 0xc67000f8, + 0x0e0bf401, +/* 0x072c: memx_info_data */ + 0x03ccc7f1, + 0x0800b7f1, +/* 0x0737: memx_info_train */ + 0xf10b0ef4, + 0xf10bccc7, +/* 0x073f: memx_info_send */ + 0xf50100b7, + 0xf8033721, +/* 0x0745: memx_recv */ + 0x01d6b000, + 0xb0980bf4, + 0x0bf400d6, +/* 0x0753: memx_init */ + 0xf800f8d8, +/* 0x0755: perf_recv */ +/* 0x0757: perf_init */ + 0xf800f800, +/* 0x0759: i2c_drive_scl */ + 0x0036b000, + 0xf1110bf4, + 0xb607e007, + 0x01d00604, + 0xf804bd00, +/* 0x076d: i2c_drive_scl_lo */ + 0xe407f100, + 0x0604b607, + 0xbd0001d0, +/* 0x077b: i2c_drive_sda */ + 0xb000f804, + 0x0bf40036, + 0xe007f111, + 0x0604b607, + 0xbd0002d0, +/* 0x078f: i2c_drive_sda_lo */ + 0xf100f804, + 0xb607e407, + 0x02d00604, + 0xf804bd00, +/* 0x079d: i2c_sense_scl */ + 0x0132f400, + 0x07c437f1, + 0xcf0634b6, + 0x31fd0033, + 0x060bf404, +/* 0x07b3: i2c_sense_scl_done */ + 0xf80131f4, +/* 0x07b5: i2c_sense_sda */ + 0x0132f400, + 0x07c437f1, + 0xcf0634b6, + 0x32fd0033, + 0x060bf404, +/* 0x07cb: i2c_sense_sda_done */ + 0xf80131f4, +/* 0x07cd: i2c_raise_scl */ + 0xf140f900, + 0xf0089847, + 0x21f50137, +/* 0x07da: i2c_raise_scl_wait */ + 0xe7f10759, + 0x21f403e8, + 0x9d21f57f, + 0x0901f407, + 0xf40142b6, +/* 0x07ee: i2c_raise_scl_done */ + 0x40fcef1b, +/* 0x07f2: i2c_start */ + 0x21f500f8, + 0x11f4079d, + 0xb521f50d, + 0x0611f407, +/* 0x0803: i2c_start_rep */ + 0xf0300ef4, + 0x21f50037, + 0x37f00759, + 0x7b21f501, + 0x0076bb07, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x21f550fc, + 0x64b607cd, + 0x1f11f404, +/* 0x0830: i2c_start_send */ + 0xf50037f0, + 0xf1077b21, + 0xf41388e7, + 0x37f07f21, + 0x5921f500, + 0x88e7f107, + 0x7f21f413, +/* 0x084c: i2c_start_out */ +/* 0x084e: i2c_stop */ + 0x37f000f8, + 0x5921f500, + 0x0037f007, + 0x077b21f5, + 0x03e8e7f1, + 0xf07f21f4, + 0x21f50137, + 0xe7f10759, + 0x21f41388, + 0x0137f07f, + 0x077b21f5, + 0x1388e7f1, 0xf87f21f4, -/* 0x06e9: memx_func_train */ -/* 0x06eb: memx_exec */ - 0xf900f800, - 0xb9d0f9e0, - 0xb2b902c1, -/* 0x06f5: memx_exec_next */ - 0x00139802, - 0xe70410b6, - 0xe701f034, - 0xb601e033, - 0x30f00132, - 0xde35980c, - 0x12b855f9, - 0xe41ef406, - 0x98f10b98, - 0xcbbbf20c, - 0xc4b7f102, - 0x06b4b607, - 0xfc00bbcf, - 0xf5e0fcd0, - 0xf8034221, -/* 0x0731: memx_info */ - 0x01c67000, -/* 0x0737: memx_info_data */ - 0xf10e0bf4, - 0xf103ccc7, - 0xf40800b7, -/* 0x0742: memx_info_train */ - 0xc7f10b0e, - 0xb7f10bcc, -/* 0x074a: memx_info_send */ - 0x21f50100, - 0x00f80342, -/* 0x0750: memx_recv */ - 0xf401d6b0, - 0xd6b0980b, - 0xd80bf400, -/* 0x075e: memx_init */ - 0x00f800f8, -/* 0x0760: perf_recv */ -/* 0x0762: perf_init */ - 0x00f800f8, -/* 0x0764: i2c_drive_scl */ - 0xf40036b0, - 0x07f1110b, - 0x04b607e0, - 0x0001d006, - 0x00f804bd, -/* 0x0778: i2c_drive_scl_lo */ - 0x07e407f1, - 0xd00604b6, - 0x04bd0001, -/* 0x0786: i2c_drive_sda */ - 0x36b000f8, - 0x110bf400, - 0x07e007f1, - 0xd00604b6, - 0x04bd0002, -/* 0x079a: i2c_drive_sda_lo */ - 0x07f100f8, - 0x04b607e4, - 0x0002d006, - 0x00f804bd, -/* 0x07a8: i2c_sense_scl */ - 0xf10132f4, - 0xb607c437, - 0x33cf0634, - 0x0431fd00, - 0xf4060bf4, -/* 0x07be: i2c_sense_scl_done */ - 0x00f80131, -/* 0x07c0: i2c_sense_sda */ - 0xf10132f4, - 0xb607c437, - 0x33cf0634, - 0x0432fd00, - 0xf4060bf4, -/* 0x07d6: i2c_sense_sda_done */ - 0x00f80131, -/* 0x07d8: i2c_raise_scl */ - 0x47f140f9, - 0x37f00898, - 0x6421f501, -/* 0x07e5: i2c_raise_scl_wait */ +/* 0x0881: i2c_bitw */ + 0x7b21f500, 0xe8e7f107, 0x7f21f403, - 0x07a821f5, - 0xb60901f4, - 0x1bf40142, -/* 0x07f9: i2c_raise_scl_done */ - 0xf840fcef, -/* 0x07fd: i2c_start */ - 0xa821f500, - 0x0d11f407, - 0x07c021f5, - 0xf40611f4, -/* 0x080e: i2c_start_rep */ - 0x37f0300e, - 0x6421f500, - 0x0137f007, - 0x078621f5, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0xd821f550, + 0xcd21f550, 0x0464b607, -/* 0x083b: i2c_start_send */ - 0xf01f11f4, - 0x21f50037, - 0xe7f10786, - 0x21f41388, - 0x0037f07f, - 0x076421f5, - 0x1388e7f1, -/* 0x0857: i2c_start_out */ - 0xf87f21f4, -/* 0x0859: i2c_stop */ - 0x0037f000, - 0x076421f5, - 0xf50037f0, - 0xf1078621, - 0xf403e8e7, + 0xf11811f4, + 0xf41388e7, 0x37f07f21, - 0x6421f501, + 0x5921f500, 0x88e7f107, 0x7f21f413, - 0xf50137f0, - 0xf1078621, - 0xf41388e7, - 0x00f87f21, -/* 0x088c: i2c_bitw */ - 0x078621f5, - 0x03e8e7f1, - 0xbb7f21f4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x07d821f5, - 0xf40464b6, - 0xe7f11811, +/* 0x08c0: i2c_bitw_out */ +/* 0x08c2: i2c_bitr */ + 0x37f000f8, + 0x7b21f501, + 0xe8e7f107, + 0x7f21f403, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xcd21f550, + 0x0464b607, + 0xf51b11f4, + 0xf007b521, + 0x21f50037, + 0xe7f10759, 0x21f41388, - 0x0037f07f, - 0x076421f5, - 0x1388e7f1, -/* 0x08cb: i2c_bitw_out */ - 0xf87f21f4, -/* 0x08cd: i2c_bitr */ - 0x0137f000, - 0x078621f5, - 0x03e8e7f1, - 0xbb7f21f4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x07d821f5, - 0xf40464b6, - 0x21f51b11, - 0x37f007c0, - 0x6421f500, - 0x88e7f107, - 0x7f21f413, - 0xf4013cf0, -/* 0x0912: i2c_bitr_done */ - 0x00f80131, -/* 0x0914: i2c_get_byte */ - 0xf00057f0, -/* 0x091a: i2c_get_byte_next */ - 0x54b60847, + 0x013cf07f, +/* 0x0907: i2c_bitr_done */ + 0xf80131f4, +/* 0x0909: i2c_get_byte */ + 0x0057f000, +/* 0x090f: i2c_get_byte_next */ + 0xb60847f0, + 0x76bb0154, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb608c221, + 0x11f40464, + 0x0553fd2b, + 0xf40142b6, + 0x37f0d81b, 0x0076bb01, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b608cd, - 0x2b11f404, - 0xb60553fd, - 0x1bf40142, - 0x0137f0d8, + 0x64b60881, +/* 0x0959: i2c_get_byte_done */ +/* 0x095b: i2c_put_byte */ + 0xf000f804, +/* 0x095e: i2c_put_byte_next */ + 0x42b60847, + 0x3854ff01, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x8c21f550, + 0x8121f550, 0x0464b608, -/* 0x0964: i2c_get_byte_done */ -/* 0x0966: i2c_put_byte */ - 0x47f000f8, -/* 0x0969: i2c_put_byte_next */ - 0x0142b608, - 0xbb3854ff, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x088c21f5, - 0xf40464b6, - 0x46b03411, - 0xd81bf400, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0xcd21f550, - 0x0464b608, - 0xbb0f11f4, - 0x36b00076, - 0x061bf401, -/* 0x09bf: i2c_put_byte_done */ - 0xf80132f4, -/* 0x09c1: i2c_addr */ - 0x0076bb00, + 0xb03411f4, + 0x1bf40046, + 0x0076bbd8, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b607fd, - 0x2911f404, - 0x012ec3e7, - 0xfd0134b6, - 0x76bb0553, + 0x64b608c2, + 0x0f11f404, + 0xb00076bb, + 0x1bf40136, + 0x0132f406, +/* 0x09b4: i2c_put_byte_done */ +/* 0x09b6: i2c_addr */ + 0x76bb00f8, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb6096621, -/* 0x0a06: i2c_addr_done */ - 0x00f80464, -/* 0x0a08: i2c_acquire_addr */ - 0xb6f8cec7, - 0xe0b702e4, - 0xee980d1c, -/* 0x0a17: i2c_acquire */ - 0xf500f800, - 0xf40a0821, - 0xd9f00421, - 0x3f21f403, -/* 0x0a26: i2c_release */ - 0x21f500f8, - 0x21f40a08, - 0x03daf004, - 0xf83f21f4, -/* 0x0a35: i2c_recv */ - 0x0132f400, - 0xb6f8c1c7, - 0x16b00214, - 0x3a1ff528, - 0xf413a001, - 0x0032980c, - 0x0ccc13a0, - 0xf4003198, - 0xd0f90231, - 0xd0f9e0f9, - 0x000067f1, - 0x100063f1, - 0xbb016792, + 0xb607f221, + 0x11f40464, + 0x2ec3e729, + 0x0134b601, + 0xbb0553fd, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x0a1721f5, - 0xfc0464b6, - 0x00d6b0d0, - 0x00b31bf5, - 0xbb0057f0, + 0x095b21f5, +/* 0x09fb: i2c_addr_done */ + 0xf80464b6, +/* 0x09fd: i2c_acquire_addr */ + 0xf8cec700, + 0xb702e4b6, + 0x980d1ce0, + 0x00f800ee, +/* 0x0a0c: i2c_acquire */ + 0x09fd21f5, + 0xf00421f4, + 0x21f403d9, +/* 0x0a1b: i2c_release */ + 0xf500f83f, + 0xf409fd21, + 0xdaf00421, + 0x3f21f403, +/* 0x0a2a: i2c_recv */ + 0x32f400f8, + 0xf8c1c701, + 0xb00214b6, + 0x1ff52816, + 0x13a0013a, + 0x32980cf4, + 0xcc13a000, + 0x0031980c, + 0xf90231f4, + 0xf9e0f9d0, + 0x0067f1d0, + 0x0063f100, + 0x01679210, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0x0c21f550, + 0x0464b60a, + 0xd6b0d0fc, + 0xb31bf500, + 0x0057f000, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xb621f550, + 0x0464b609, + 0x00d011f5, + 0xbbe0c5c7, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x09c121f5, + 0x095b21f5, 0xf50464b6, - 0xc700d011, - 0x76bbe0c5, + 0xf000ad11, + 0x76bb0157, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb6096621, + 0xb609b621, 0x11f50464, - 0x57f000ad, - 0x0076bb01, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b609c1, - 0x8a11f504, - 0x0076bb00, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b60914, - 0x6a11f404, - 0xbbe05bcb, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x085921f5, - 0xb90464b6, - 0x74bd025b, -/* 0x0b3b: i2c_recv_not_rd08 */ - 0xb0430ef4, - 0x1bf401d6, - 0x0057f03d, - 0x09c121f5, - 0xc73311f4, - 0x21f5e0c5, - 0x11f40966, - 0x0057f029, - 0x09c121f5, - 0xc71f11f4, - 0x21f5e0b5, - 0x11f40966, - 0x5921f515, - 0xc774bd08, - 0x1bf408c5, - 0x0232f409, -/* 0x0b7b: i2c_recv_not_wr08 */ -/* 0x0b7b: i2c_recv_done */ - 0xc7030ef4, - 0x21f5f8ce, - 0xe0fc0a26, - 0x12f4d0fc, - 0x027cb90a, - 0x034221f5, -/* 0x0b90: i2c_recv_exit */ -/* 0x0b92: i2c_init */ + 0x76bb008a, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb6090921, + 0x11f40464, + 0xe05bcb6a, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0x4e21f550, + 0x0464b608, + 0xbd025bb9, + 0x430ef474, +/* 0x0b30: i2c_recv_not_rd08 */ + 0xf401d6b0, + 0x57f03d1b, + 0xb621f500, + 0x3311f409, + 0xf5e0c5c7, + 0xf4095b21, + 0x57f02911, + 0xb621f500, + 0x1f11f409, + 0xf5e0b5c7, + 0xf4095b21, + 0x21f51511, + 0x74bd084e, + 0xf408c5c7, + 0x32f4091b, + 0x030ef402, +/* 0x0b70: i2c_recv_not_wr08 */ +/* 0x0b70: i2c_recv_done */ + 0xf5f8cec7, + 0xfc0a1b21, + 0xf4d0fce0, + 0x7cb90a12, + 0x3721f502, +/* 0x0b85: i2c_recv_exit */ +/* 0x0b87: i2c_init */ + 0xf800f803, +/* 0x0b89: test_recv */ + 0xd817f100, + 0x0614b605, + 0xb60011cf, + 0x07f10110, + 0x04b605d8, + 0x0001d006, + 0xe7f104bd, + 0xe3f1d900, + 0x21f5134f, + 0x00f80257, +/* 0x0bb0: test_init */ + 0x0800e7f1, + 0x025721f5, +/* 0x0bba: idle_recv */ 0x00f800f8, -/* 0x0b94: test_recv */ - 0x05d817f1, - 0xcf0614b6, - 0x10b60011, - 0xd807f101, - 0x0604b605, - 0xbd0001d0, - 0x00e7f104, - 0x4fe3f1d9, - 0x6221f513, -/* 0x0bbb: test_init */ - 0xf100f802, - 0xf50800e7, - 0xf8026221, -/* 0x0bc5: idle_recv */ -/* 0x0bc7: idle */ - 0xf400f800, - 0x17f10031, - 0x14b605d4, - 0x0011cf06, - 0xf10110b6, - 0xb605d407, - 0x01d00604, -/* 0x0be3: idle_loop */ - 0xf004bd00, - 0x32f45817, -/* 0x0be9: idle_proc */ -/* 0x0be9: idle_proc_exec */ - 0xb910f902, - 0x21f5021e, - 0x10fc034b, - 0xf40911f4, - 0x0ef40231, -/* 0x0bfd: idle_proc_next */ - 0x5810b6ef, - 0xf4061fb8, - 0x02f4e61b, - 0x0028f4dd, - 0x00bb0ef4, +/* 0x0bbc: idle */ + 0xf10031f4, + 0xb605d417, + 0x11cf0614, + 0x0110b600, + 0x05d407f1, + 0xd00604b6, + 0x04bd0001, +/* 0x0bd8: idle_loop */ + 0xf45817f0, +/* 0x0bde: idle_proc */ +/* 0x0bde: idle_proc_exec */ + 0x10f90232, + 0xf5021eb9, + 0xfc034021, + 0x0911f410, + 0xf40231f4, +/* 0x0bf2: idle_proc_next */ + 0x10b6ef0e, + 0x061fb858, + 0xf4e61bf4, + 0x28f4dd02, + 0xbb0ef400, + 0x00000000, + 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h index 31552af9b06e..7bf6b39ed205 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h @@ -24,8 +24,8 @@ uint32_t gf119_pmu_data[] = { 0x00000000, /* 0x0058: proc_list_head */ 0x54534f48, - 0x0000049d, - 0x00000446, + 0x00000492, + 0x0000043b, 0x00000000, 0x00000000, 0x00000000, @@ -46,8 +46,8 @@ uint32_t gf119_pmu_data[] = { 0x00000000, 0x00000000, 0x584d454d, - 0x0000068b, - 0x0000067d, + 0x00000680, + 0x00000672, 0x00000000, 0x00000000, 0x00000000, @@ -68,8 +68,8 @@ uint32_t gf119_pmu_data[] = { 0x00000000, 0x00000000, 0x46524550, - 0x0000068f, - 0x0000068d, + 0x00000684, + 0x00000682, 0x00000000, 0x00000000, 0x00000000, @@ -90,8 +90,8 @@ uint32_t gf119_pmu_data[] = { 0x00000000, 0x00000000, 0x5f433249, - 0x00000aaa, - 0x0000094d, + 0x00000a9f, + 0x00000942, 0x00000000, 0x00000000, 0x00000000, @@ -112,8 +112,8 @@ uint32_t gf119_pmu_data[] = { 0x00000000, 0x00000000, 0x54534554, - 0x00000acd, - 0x00000aac, + 0x00000ac2, + 0x00000aa1, 0x00000000, 0x00000000, 0x00000000, @@ -134,8 +134,8 @@ uint32_t gf119_pmu_data[] = { 0x00000000, 0x00000000, 0x454c4449, - 0x00000ad9, - 0x00000ad7, + 0x00000ace, + 0x00000acc, 0x00000000, 0x00000000, 0x00000000, @@ -229,26 +229,26 @@ uint32_t gf119_pmu_data[] = { /* 0x0370: memx_func_head */ 0x00000001, 0x00000000, - 0x000004d3, + 0x000004c8, /* 0x037c: memx_func_next */ 0x00000002, 0x00000000, - 0x00000554, + 0x00000549, 0x00000003, 0x00000002, - 0x000005d8, + 0x000005cd, 0x00040004, 0x00000000, - 0x000005f4, + 0x000005e9, 0x00010005, 0x00000000, - 0x0000060e, + 0x00000603, 0x00010006, 0x00000000, - 0x000005d3, + 0x000005c8, 0x00000007, 0x00000000, - 0x00000619, + 0x0000060e, /* 0x03c4: memx_func_tail */ /* 0x03c4: memx_ts_start */ 0x00000000, @@ -916,7 +916,7 @@ uint32_t gf119_pmu_data[] = { }; uint32_t gf119_pmu_code[] = { - 0x034d0ef5, + 0x03420ef5, /* 0x0004: rd32 */ 0x07a007f1, 0xbd000ed0, @@ -977,7 +977,7 @@ uint32_t gf119_pmu_code[] = { 0xbb9a0a98, 0x1cf4029a, 0x01d7f00f, - 0x028c21f5, + 0x028121f5, 0x0ef494bd, /* 0x00d5: intr_watchdog_next_time */ 0x9b0a9815, @@ -1025,716 +1025,714 @@ uint32_t gf119_pmu_code[] = { 0xf14f48e7, 0xf05453e3, 0x21f500d7, - 0xc0fc02f1, + 0xc0fc02e6, 0x04c007f1, 0xbd000cd0, /* 0x0185: intr_subintr_skip_fifo */ 0x8807f104, 0x0009d006, /* 0x018e: intr_skip_subintr */ - 0x89c404bd, - 0x070bf420, - 0xffbfa4f1, -/* 0x0198: intr_skip_pause */ - 0xf44089c4, - 0xa4f1070b, -/* 0x01a2: intr_skip_user0 */ - 0x07f0ffbf, - 0x0008d004, - 0x80fc04bd, - 0xfc0088fe, - 0xfce0fcf0, - 0xfcc0fcd0, - 0xfca0fcb0, - 0xfc80fc90, - 0x0032f400, -/* 0x01c6: ticks_from_ns */ - 0xc0f901f8, - 0xd7f1b0f9, - 0xd3f00144, - 0xb321f500, - 0xe8ccec03, - 0x00b4b003, - 0xec120bf4, - 0xf103e8ee, - 0xf00144d7, - 0x21f500d3, -/* 0x01ee: ticks_from_ns_quit */ - 0xceb903b3, - 0xfcb0fc02, -/* 0x01f7: ticks_from_us */ - 0xf900f8c0, + 0x97f104bd, + 0x90bd00e0, + 0xf00489fd, + 0x08d00407, + 0xfc04bd00, + 0x0088fe80, + 0xe0fcf0fc, + 0xc0fcd0fc, + 0xa0fcb0fc, + 0x80fc90fc, + 0x32f400fc, +/* 0x01bb: ticks_from_ns */ + 0xf901f800, 0xf1b0f9c0, 0xf00144d7, 0x21f500d3, - 0xceb903b3, - 0x00b4b002, - 0xbd050bf4, -/* 0x0211: ticks_from_us_quit */ - 0xfcb0fce4, -/* 0x0217: ticks_to_us */ - 0xf100f8c0, - 0xf00144d7, - 0xedff00d3, -/* 0x0223: timer */ - 0xf900f8ec, - 0xf480f990, - 0xf8981032, - 0x0086b003, - 0xbd531cf4, - 0x3807f084, - 0xbd0008d0, - 0x3487f004, - 0x980088cf, - 0x98bb9a09, - 0x00e9bb02, - 0xf003fe80, - 0x88cf0887, - 0x0284f000, - 0xf0201bf4, - 0x88cf3487, - 0x06e0b800, - 0xb8090bf4, - 0x1cf406e8, -/* 0x026d: timer_reset */ - 0x3407f00e, - 0xbd000ed0, - 0x9a0e8004, -/* 0x0278: timer_enable */ - 0xf00187f0, - 0x08d03807, -/* 0x0283: timer_done */ - 0xf404bd00, - 0x80fc1031, - 0x00f890fc, -/* 0x028c: send_proc */ - 0x90f980f9, - 0x9805e898, - 0x86f004e9, - 0x0689b804, - 0xc42a0bf4, - 0x88940398, - 0x1880b604, - 0x98008ebb, - 0x8a8000fa, - 0x018d8000, - 0x80028c80, - 0x90b6038b, - 0x0794f001, - 0xf404e980, -/* 0x02c6: send_done */ - 0x90fc0231, - 0x00f880fc, -/* 0x02cc: find */ - 0x87f080f9, - 0x0131f458, -/* 0x02d4: find_loop */ - 0xb8008a98, - 0x0bf406ae, - 0x5880b610, - 0x026886b1, - 0xf4f01bf4, -/* 0x02ea: find_done */ - 0x8eb90132, - 0xf880fc02, -/* 0x02f1: send */ - 0xcc21f500, - 0x9701f402, -/* 0x02fa: recv */ - 0x90f900f8, - 0xe89880f9, - 0x04e99805, - 0xb80132f4, - 0x0bf40689, - 0x0389c43d, - 0xf00180b6, - 0xe8800784, - 0x02ea9805, - 0x8ffef0f9, - 0xb9f0f901, - 0x999402ef, - 0x00e9bb04, - 0x9818e0b6, - 0xec9803eb, - 0x01ed9802, - 0xf900ee98, - 0xfef0fca5, - 0x31f400f8, -/* 0x0347: recv_done */ - 0xfcf0fc01, + 0xccec03a8, + 0xb4b003e8, + 0x120bf400, + 0x03e8eeec, + 0x0144d7f1, + 0xf500d3f0, +/* 0x01e3: ticks_from_ns_quit */ + 0xb903a821, + 0xb0fc02ce, + 0x00f8c0fc, +/* 0x01ec: ticks_from_us */ + 0xb0f9c0f9, + 0x0144d7f1, + 0xf500d3f0, + 0xb903a821, + 0xb4b002ce, + 0x050bf400, +/* 0x0206: ticks_from_us_quit */ + 0xb0fce4bd, + 0x00f8c0fc, +/* 0x020c: ticks_to_us */ + 0x0144d7f1, + 0xff00d3f0, + 0x00f8eced, +/* 0x0218: timer */ + 0x80f990f9, + 0x981032f4, + 0x86b003f8, + 0x531cf400, + 0x07f084bd, + 0x0008d038, + 0x87f004bd, + 0x0088cf34, + 0xbb9a0998, + 0xe9bb0298, + 0x03fe8000, + 0xcf0887f0, + 0x84f00088, + 0x201bf402, + 0xcf3487f0, + 0xe0b80088, + 0x090bf406, + 0xf406e8b8, +/* 0x0262: timer_reset */ + 0x07f00e1c, + 0x000ed034, + 0x0e8004bd, +/* 0x026d: timer_enable */ + 0x0187f09a, + 0xd03807f0, + 0x04bd0008, +/* 0x0278: timer_done */ + 0xfc1031f4, 0xf890fc80, -/* 0x034d: init */ - 0x0817f100, - 0x0011cf01, - 0x010911e7, - 0xfe0814b6, - 0x17f10014, - 0x13f000e0, - 0x1c07f000, +/* 0x0281: send_proc */ + 0xf980f900, + 0x05e89890, + 0xf004e998, + 0x89b80486, + 0x2a0bf406, + 0x940398c4, + 0x80b60488, + 0x008ebb18, + 0x8000fa98, + 0x8d80008a, + 0x028c8001, + 0xb6038b80, + 0x94f00190, + 0x04e98007, +/* 0x02bb: send_done */ + 0xfc0231f4, + 0xf880fc90, +/* 0x02c1: find */ + 0xf080f900, + 0x31f45887, +/* 0x02c9: find_loop */ + 0x008a9801, + 0xf406aeb8, + 0x80b6100b, + 0x6886b158, + 0xf01bf402, +/* 0x02df: find_done */ + 0xb90132f4, + 0x80fc028e, +/* 0x02e6: send */ + 0x21f500f8, + 0x01f402c1, +/* 0x02ef: recv */ + 0xf900f897, + 0x9880f990, + 0xe99805e8, + 0x0132f404, + 0xf40689b8, + 0x89c43d0b, + 0x0180b603, + 0x800784f0, + 0xea9805e8, + 0xfef0f902, + 0xf0f9018f, + 0x9402efb9, + 0xe9bb0499, + 0x18e0b600, + 0x9803eb98, + 0xed9802ec, + 0x00ee9801, + 0xf0fca5f9, + 0xf400f8fe, + 0xf0fc0131, +/* 0x033c: recv_done */ + 0x90fc80fc, +/* 0x0342: init */ + 0x17f100f8, + 0x11cf0108, + 0x0911e700, + 0x0814b601, + 0xf10014fe, + 0xf000e017, + 0x07f00013, + 0x0001d01c, + 0x17f004bd, + 0x1407f0ff, 0xbd0001d0, - 0xff17f004, - 0xd01407f0, + 0x0217f004, + 0x080015f1, + 0xd01007f0, 0x04bd0001, - 0xf10217f0, - 0xf0080015, - 0x01d01007, - 0xf104bd00, - 0xf000f617, - 0x10fe0013, - 0x1031f400, - 0xf00117f0, - 0x01d03807, - 0xf004bd00, -/* 0x03a2: init_proc */ - 0xf19858f7, - 0x0016b001, - 0xf9fa0bf4, - 0x58f0b615, -/* 0x03b3: mulu32_32_64 */ - 0xf9f20ef4, - 0xf920f910, - 0x9540f930, - 0xd29510e1, - 0xbdc4bd10, - 0xc0edffb4, - 0xb9301dff, - 0x34f10234, - 0x34b6ffff, - 0x1045b610, - 0xbb00c3bb, - 0xe2ff01b4, - 0x0234b930, - 0xffff34f1, - 0xb61034b6, - 0xc3bb1045, - 0x01b4bb00, - 0xbb3012ff, - 0x40fc00b3, - 0x20fc30fc, - 0x00f810fc, -/* 0x0404: host_send */ - 0x04b017f1, - 0xf10011cf, - 0xcf04a027, - 0x12b80022, - 0x2f0bf406, - 0x94071ec4, - 0xe0b704ee, - 0xeb980270, - 0x02ec9803, - 0x9801ed98, - 0x21f500ee, - 0x10b602f1, - 0x0f1ec401, - 0x04b007f1, - 0xbd000ed0, - 0xc30ef404, -/* 0x0444: host_send_done */ -/* 0x0446: host_recv */ - 0x17f100f8, - 0x13f14e49, - 0xe1b85254, - 0xb30bf406, -/* 0x0454: host_recv_wait */ - 0x04cc17f1, - 0xf10011cf, - 0xcf04c827, - 0x16f00022, - 0x0612b808, - 0xc4ec0bf4, - 0x34b60723, - 0xf030b704, - 0x033b8002, - 0x80023c80, - 0x3e80013d, - 0x0120b600, - 0xf10f24f0, - 0xd004c807, + 0x00f617f1, + 0xfe0013f0, + 0x31f40010, + 0x0117f010, + 0xd03807f0, + 0x04bd0001, +/* 0x0397: init_proc */ + 0x9858f7f0, + 0x16b001f1, + 0xfa0bf400, + 0xf0b615f9, + 0xf20ef458, +/* 0x03a8: mulu32_32_64 */ + 0x20f910f9, + 0x40f930f9, + 0x9510e195, + 0xc4bd10d2, + 0xedffb4bd, + 0x301dffc0, + 0xf10234b9, + 0xb6ffff34, + 0x45b61034, + 0x00c3bb10, + 0xff01b4bb, + 0x34b930e2, + 0xff34f102, + 0x1034b6ff, + 0xbb1045b6, + 0xb4bb00c3, + 0x3012ff01, + 0xfc00b3bb, + 0xfc30fc40, + 0xf810fc20, +/* 0x03f9: host_send */ + 0xb017f100, + 0x0011cf04, + 0x04a027f1, + 0xb80022cf, + 0x0bf40612, + 0x071ec42f, + 0xb704ee94, + 0x980270e0, + 0xec9803eb, + 0x01ed9802, + 0xf500ee98, + 0xb602e621, + 0x1ec40110, + 0xb007f10f, + 0x000ed004, + 0x0ef404bd, +/* 0x0439: host_send_done */ +/* 0x043b: host_recv */ + 0xf100f8c3, + 0xf14e4917, + 0xb8525413, + 0x0bf406e1, +/* 0x0449: host_recv_wait */ + 0xcc17f1b3, + 0x0011cf04, + 0x04c827f1, + 0xf00022cf, + 0x12b80816, + 0xec0bf406, + 0xb60723c4, + 0x30b70434, + 0x3b8002f0, + 0x023c8003, + 0x80013d80, + 0x20b6003e, + 0x0f24f001, + 0x04c807f1, + 0xbd0002d0, + 0x4027f004, + 0xd00007f0, 0x04bd0002, - 0xf04027f0, - 0x02d00007, - 0xf804bd00, -/* 0x049d: host_init */ - 0x8017f100, - 0x1014b600, - 0x027015f1, - 0x04d007f1, - 0xbd0001d0, - 0x8017f104, - 0x1014b600, - 0x02f015f1, - 0x04dc07f1, - 0xbd0001d0, - 0x0117f004, - 0x04c407f1, - 0xbd0001d0, -/* 0x04d3: memx_func_enter */ - 0xf100f804, - 0xf1162067, - 0xf1f55d77, +/* 0x0492: host_init */ + 0x17f100f8, + 0x14b60080, + 0x7015f110, + 0xd007f102, + 0x0001d004, + 0x17f104bd, + 0x14b60080, + 0xf015f110, + 0xdc07f102, + 0x0001d004, + 0x17f004bd, + 0xc407f101, + 0x0001d004, + 0x00f804bd, +/* 0x04c8: memx_func_enter */ + 0x162067f1, + 0xf55d77f1, + 0xffff73f1, + 0xf4026eb9, + 0xd8b90421, + 0x0487fd02, + 0x80f960f9, + 0xe0fcd0fc, + 0xf13321f4, + 0xf1fffe77, 0xb9ffff73, 0x21f4026e, 0x02d8b904, 0xf90487fd, 0xfc80f960, 0xf4e0fcd0, - 0x77f13321, - 0x73f1fffe, - 0x6eb9ffff, + 0x67f13321, + 0x6eb926f0, 0x0421f402, 0xfd02d8b9, 0x60f90487, 0xd0fc80f9, 0x21f4e0fc, - 0xf067f133, - 0x026eb926, - 0xb90421f4, - 0x87fd02d8, - 0xf960f904, - 0xfcd0fc80, - 0x3321f4e0, - 0xf10467f0, - 0xd007e007, - 0x04bd0006, -/* 0x053c: memx_func_enter_wait */ - 0x07c067f1, - 0xf00066cf, - 0x0bf40464, - 0x2c67f0f6, - 0x800066cf, - 0x00f8f106, -/* 0x0554: memx_func_leave */ - 0xcf2c67f0, - 0x06800066, - 0x0467f0f2, - 0x07e407f1, + 0x0467f033, + 0x07e007f1, 0xbd0006d0, -/* 0x0569: memx_func_leave_wait */ +/* 0x0531: memx_func_enter_wait */ 0xc067f104, 0x0066cf07, 0xf40464f0, - 0x67f1f61b, - 0x77f126f0, - 0x73f00001, - 0x026eb900, - 0xb90421f4, - 0x87fd02d8, - 0xf960f905, - 0xfcd0fc80, - 0x3321f4e0, - 0x162067f1, - 0xf4026eb9, - 0xd8b90421, - 0x0587fd02, - 0x80f960f9, - 0xe0fcd0fc, - 0xf13321f4, - 0xf00aa277, + 0x67f0f60b, + 0x0066cf2c, + 0xf8f10680, +/* 0x0549: memx_func_leave */ + 0x2c67f000, + 0x800066cf, + 0x67f0f206, + 0xe407f104, + 0x0006d007, +/* 0x055e: memx_func_leave_wait */ + 0x67f104bd, + 0x66cf07c0, + 0x0464f000, + 0xf1f61bf4, + 0xf126f067, + 0xf0000177, 0x6eb90073, 0x0421f402, 0xfd02d8b9, 0x60f90587, 0xd0fc80f9, 0x21f4e0fc, -/* 0x05d3: memx_func_wait_vblank */ - 0xb600f833, - 0x00f80410, -/* 0x05d8: memx_func_wr32 */ - 0x98001698, - 0x10b60115, - 0xf960f908, - 0xfcd0fc50, + 0x2067f133, + 0x026eb916, + 0xb90421f4, + 0x87fd02d8, + 0xf960f905, + 0xfcd0fc80, 0x3321f4e0, - 0xf40242b6, - 0x00f8e91b, -/* 0x05f4: memx_func_wait */ - 0xcf2c87f0, - 0x1e980088, - 0x011d9800, - 0x98021c98, - 0x10b6031b, - 0x8621f410, -/* 0x060e: memx_func_delay */ - 0x1e9800f8, + 0x0aa277f1, + 0xb90073f0, + 0x21f4026e, + 0x02d8b904, + 0xf90587fd, + 0xfc80f960, + 0xf4e0fcd0, + 0x00f83321, +/* 0x05c8: memx_func_wait_vblank */ + 0xf80410b6, +/* 0x05cd: memx_func_wr32 */ + 0x00169800, + 0xb6011598, + 0x60f90810, + 0xd0fc50f9, + 0x21f4e0fc, + 0x0242b633, + 0xf8e91bf4, +/* 0x05e9: memx_func_wait */ + 0x2c87f000, + 0x980088cf, + 0x1d98001e, + 0x021c9801, + 0xb6031b98, + 0x21f41010, +/* 0x0603: memx_func_delay */ + 0x9800f886, + 0x10b6001e, + 0x6721f404, +/* 0x060e: memx_func_train */ + 0x00f800f8, +/* 0x0610: memx_exec */ + 0xd0f9e0f9, + 0xb902c1b9, +/* 0x061a: memx_exec_next */ + 0x139802b2, 0x0410b600, - 0xf86721f4, -/* 0x0619: memx_func_train */ -/* 0x061b: memx_exec */ - 0xf900f800, - 0xb9d0f9e0, - 0xb2b902c1, -/* 0x0625: memx_exec_next */ - 0x00139802, - 0xe70410b6, - 0xe701f034, - 0xb601e033, - 0x30f00132, - 0xde35980c, - 0x12b855f9, - 0xe41ef406, - 0x98f10b98, - 0xcbbbf20c, - 0xc4b7f102, - 0x00bbcf07, - 0xe0fcd0fc, - 0x02f121f5, -/* 0x065e: memx_info */ - 0xc67000f8, - 0x0e0bf401, -/* 0x0664: memx_info_data */ - 0x03ccc7f1, - 0x0800b7f1, -/* 0x066f: memx_info_train */ - 0xf10b0ef4, - 0xf10bccc7, -/* 0x0677: memx_info_send */ - 0xf50100b7, - 0xf802f121, -/* 0x067d: memx_recv */ - 0x01d6b000, - 0xb09b0bf4, - 0x0bf400d6, -/* 0x068b: memx_init */ - 0xf800f8d8, -/* 0x068d: perf_recv */ -/* 0x068f: perf_init */ - 0xf800f800, -/* 0x0691: i2c_drive_scl */ - 0x0036b000, - 0xf10e0bf4, - 0xd007e007, + 0x01f034e7, + 0x01e033e7, + 0xf00132b6, + 0x35980c30, + 0xb855f9de, + 0x1ef40612, + 0xf10b98e4, + 0xbbf20c98, + 0xb7f102cb, + 0xbbcf07c4, + 0xfcd0fc00, + 0xe621f5e0, +/* 0x0653: memx_info */ + 0x7000f802, + 0x0bf401c6, +/* 0x0659: memx_info_data */ + 0xccc7f10e, + 0x00b7f103, + 0x0b0ef408, +/* 0x0664: memx_info_train */ + 0x0bccc7f1, + 0x0100b7f1, +/* 0x066c: memx_info_send */ + 0x02e621f5, +/* 0x0672: memx_recv */ + 0xd6b000f8, + 0x9b0bf401, + 0xf400d6b0, + 0x00f8d80b, +/* 0x0680: memx_init */ +/* 0x0682: perf_recv */ + 0x00f800f8, +/* 0x0684: perf_init */ +/* 0x0686: i2c_drive_scl */ + 0x36b000f8, + 0x0e0bf400, + 0x07e007f1, + 0xbd0001d0, +/* 0x0697: i2c_drive_scl_lo */ + 0xf100f804, + 0xd007e407, 0x04bd0001, -/* 0x06a2: i2c_drive_scl_lo */ - 0x07f100f8, - 0x01d007e4, - 0xf804bd00, -/* 0x06ad: i2c_drive_sda */ - 0x0036b000, - 0xf10e0bf4, - 0xd007e007, +/* 0x06a2: i2c_drive_sda */ + 0x36b000f8, + 0x0e0bf400, + 0x07e007f1, + 0xbd0002d0, +/* 0x06b3: i2c_drive_sda_lo */ + 0xf100f804, + 0xd007e407, 0x04bd0002, -/* 0x06be: i2c_drive_sda_lo */ - 0x07f100f8, - 0x02d007e4, - 0xf804bd00, -/* 0x06c9: i2c_sense_scl */ - 0x0132f400, - 0x07c437f1, - 0xfd0033cf, - 0x0bf40431, - 0x0131f406, -/* 0x06dc: i2c_sense_scl_done */ -/* 0x06de: i2c_sense_sda */ +/* 0x06be: i2c_sense_scl */ 0x32f400f8, 0xc437f101, 0x0033cf07, - 0xf40432fd, + 0xf40431fd, 0x31f4060b, -/* 0x06f1: i2c_sense_sda_done */ -/* 0x06f3: i2c_raise_scl */ - 0xf900f801, - 0x9847f140, - 0x0137f008, - 0x069121f5, -/* 0x0700: i2c_raise_scl_wait */ - 0x03e8e7f1, - 0xf56721f4, - 0xf406c921, - 0x42b60901, - 0xef1bf401, -/* 0x0714: i2c_raise_scl_done */ - 0x00f840fc, -/* 0x0718: i2c_start */ - 0x06c921f5, - 0xf50d11f4, - 0xf406de21, - 0x0ef40611, -/* 0x0729: i2c_start_rep */ - 0x0037f030, - 0x069121f5, +/* 0x06d1: i2c_sense_scl_done */ +/* 0x06d3: i2c_sense_sda */ + 0xf400f801, + 0x37f10132, + 0x33cf07c4, + 0x0432fd00, + 0xf4060bf4, +/* 0x06e6: i2c_sense_sda_done */ + 0x00f80131, +/* 0x06e8: i2c_raise_scl */ + 0x47f140f9, + 0x37f00898, + 0x8621f501, +/* 0x06f5: i2c_raise_scl_wait */ + 0xe8e7f106, + 0x6721f403, + 0x06be21f5, + 0xb60901f4, + 0x1bf40142, +/* 0x0709: i2c_raise_scl_done */ + 0xf840fcef, +/* 0x070d: i2c_start */ + 0xbe21f500, + 0x0d11f406, + 0x06d321f5, + 0xf40611f4, +/* 0x071e: i2c_start_rep */ + 0x37f0300e, + 0x8621f500, + 0x0137f006, + 0x06a221f5, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xe821f550, + 0x0464b606, +/* 0x074b: i2c_start_send */ + 0xf01f11f4, + 0x21f50037, + 0xe7f106a2, + 0x21f41388, + 0x0037f067, + 0x068621f5, + 0x1388e7f1, +/* 0x0767: i2c_start_out */ + 0xf86721f4, +/* 0x0769: i2c_stop */ + 0x0037f000, + 0x068621f5, + 0xf50037f0, + 0xf106a221, + 0xf403e8e7, + 0x37f06721, + 0x8621f501, + 0x88e7f106, + 0x6721f413, 0xf50137f0, - 0xbb06ad21, + 0xf106a221, + 0xf41388e7, + 0x00f86721, +/* 0x079c: i2c_bitw */ + 0x06a221f5, + 0x03e8e7f1, + 0xbb6721f4, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x06f321f5, + 0x06e821f5, 0xf40464b6, -/* 0x0756: i2c_start_send */ - 0x37f01f11, - 0xad21f500, - 0x88e7f106, - 0x6721f413, - 0xf50037f0, - 0xf1069121, - 0xf41388e7, -/* 0x0772: i2c_start_out */ - 0x00f86721, -/* 0x0774: i2c_stop */ - 0xf50037f0, - 0xf0069121, - 0x21f50037, - 0xe7f106ad, - 0x21f403e8, - 0x0137f067, - 0x069121f5, - 0x1388e7f1, - 0xf06721f4, - 0x21f50137, - 0xe7f106ad, + 0xe7f11811, 0x21f41388, -/* 0x07a7: i2c_bitw */ - 0xf500f867, - 0xf106ad21, - 0xf403e8e7, - 0x76bb6721, - 0x0465b600, - 0x659450f9, - 0x0256bb04, - 0x75fd50bd, - 0xf550fc04, - 0xb606f321, - 0x11f40464, - 0x88e7f118, - 0x6721f413, - 0xf50037f0, - 0xf1069121, - 0xf41388e7, -/* 0x07e6: i2c_bitw_out */ - 0x00f86721, -/* 0x07e8: i2c_bitr */ - 0xf50137f0, - 0xf106ad21, - 0xf403e8e7, - 0x76bb6721, - 0x0465b600, - 0x659450f9, - 0x0256bb04, - 0x75fd50bd, - 0xf550fc04, - 0xb606f321, - 0x11f40464, - 0xde21f51b, - 0x0037f006, - 0x069121f5, + 0x0037f067, + 0x068621f5, 0x1388e7f1, - 0xf06721f4, - 0x31f4013c, -/* 0x082d: i2c_bitr_done */ -/* 0x082f: i2c_get_byte */ - 0xf000f801, - 0x47f00057, -/* 0x0835: i2c_get_byte_next */ - 0x0154b608, +/* 0x07db: i2c_bitw_out */ + 0xf86721f4, +/* 0x07dd: i2c_bitr */ + 0x0137f000, + 0x06a221f5, + 0x03e8e7f1, + 0xbb6721f4, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x06e821f5, + 0xf40464b6, + 0x21f51b11, + 0x37f006d3, + 0x8621f500, + 0x88e7f106, + 0x6721f413, + 0xf4013cf0, +/* 0x0822: i2c_bitr_done */ + 0x00f80131, +/* 0x0824: i2c_get_byte */ + 0xf00057f0, +/* 0x082a: i2c_get_byte_next */ + 0x54b60847, + 0x0076bb01, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x21f550fc, + 0x64b607dd, + 0x2b11f404, + 0xb60553fd, + 0x1bf40142, + 0x0137f0d8, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0xe821f550, + 0x9c21f550, 0x0464b607, - 0xfd2b11f4, - 0x42b60553, - 0xd81bf401, - 0xbb0137f0, +/* 0x0874: i2c_get_byte_done */ +/* 0x0876: i2c_put_byte */ + 0x47f000f8, +/* 0x0879: i2c_put_byte_next */ + 0x0142b608, + 0xbb3854ff, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x07a721f5, -/* 0x087f: i2c_get_byte_done */ - 0xf80464b6, -/* 0x0881: i2c_put_byte */ - 0x0847f000, -/* 0x0884: i2c_put_byte_next */ - 0xff0142b6, - 0x76bb3854, - 0x0465b600, - 0x659450f9, - 0x0256bb04, - 0x75fd50bd, - 0xf550fc04, - 0xb607a721, - 0x11f40464, - 0x0046b034, - 0xbbd81bf4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x07e821f5, + 0x079c21f5, 0xf40464b6, - 0x76bb0f11, - 0x0136b000, - 0xf4061bf4, -/* 0x08da: i2c_put_byte_done */ - 0x00f80132, -/* 0x08dc: i2c_addr */ + 0x46b03411, + 0xd81bf400, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x1821f550, + 0xdd21f550, 0x0464b607, - 0xe72911f4, - 0xb6012ec3, - 0x53fd0134, - 0x0076bb05, + 0xbb0f11f4, + 0x36b00076, + 0x061bf401, +/* 0x08cf: i2c_put_byte_done */ + 0xf80132f4, +/* 0x08d1: i2c_addr */ + 0x0076bb00, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b60881, -/* 0x0921: i2c_addr_done */ -/* 0x0923: i2c_acquire_addr */ - 0xc700f804, - 0xe4b6f8ce, - 0x14e0b705, -/* 0x092f: i2c_acquire */ - 0xf500f8d0, - 0xf4092321, - 0xd9f00421, + 0x64b6070d, + 0x2911f404, + 0x012ec3e7, + 0xfd0134b6, + 0x76bb0553, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb6087621, +/* 0x0916: i2c_addr_done */ + 0x00f80464, +/* 0x0918: i2c_acquire_addr */ + 0xb6f8cec7, + 0xe0b705e4, + 0x00f8d014, +/* 0x0924: i2c_acquire */ + 0x091821f5, + 0xf00421f4, + 0x21f403d9, +/* 0x0933: i2c_release */ + 0xf500f833, + 0xf4091821, + 0xdaf00421, 0x3321f403, -/* 0x093e: i2c_release */ - 0x21f500f8, - 0x21f40923, - 0x03daf004, - 0xf83321f4, -/* 0x094d: i2c_recv */ - 0x0132f400, - 0xb6f8c1c7, - 0x16b00214, - 0x3a1ff528, - 0xf413a001, - 0x0032980c, - 0x0ccc13a0, - 0xf4003198, - 0xd0f90231, - 0xd0f9e0f9, - 0x000067f1, - 0x100063f1, - 0xbb016792, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x092f21f5, - 0xfc0464b6, - 0x00d6b0d0, - 0x00b31bf5, - 0xbb0057f0, +/* 0x0942: i2c_recv */ + 0x32f400f8, + 0xf8c1c701, + 0xb00214b6, + 0x1ff52816, + 0x13a0013a, + 0x32980cf4, + 0xcc13a000, + 0x0031980c, + 0xf90231f4, + 0xf9e0f9d0, + 0x0067f1d0, + 0x0063f100, + 0x01679210, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0x2421f550, + 0x0464b609, + 0xd6b0d0fc, + 0xb31bf500, + 0x0057f000, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xd121f550, + 0x0464b608, + 0x00d011f5, + 0xbbe0c5c7, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x08dc21f5, + 0x087621f5, 0xf50464b6, - 0xc700d011, - 0x76bbe0c5, + 0xf000ad11, + 0x76bb0157, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb6088121, + 0xb608d121, 0x11f50464, - 0x57f000ad, - 0x0076bb01, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b608dc, - 0x8a11f504, - 0x0076bb00, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b6082f, - 0x6a11f404, - 0xbbe05bcb, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x077421f5, - 0xb90464b6, - 0x74bd025b, -/* 0x0a53: i2c_recv_not_rd08 */ - 0xb0430ef4, - 0x1bf401d6, - 0x0057f03d, - 0x08dc21f5, - 0xc73311f4, - 0x21f5e0c5, - 0x11f40881, - 0x0057f029, - 0x08dc21f5, - 0xc71f11f4, - 0x21f5e0b5, - 0x11f40881, - 0x7421f515, - 0xc774bd07, - 0x1bf408c5, - 0x0232f409, -/* 0x0a93: i2c_recv_not_wr08 */ -/* 0x0a93: i2c_recv_done */ - 0xc7030ef4, - 0x21f5f8ce, - 0xe0fc093e, - 0x12f4d0fc, - 0x027cb90a, - 0x02f121f5, -/* 0x0aa8: i2c_recv_exit */ -/* 0x0aaa: i2c_init */ - 0x00f800f8, -/* 0x0aac: test_recv */ - 0x05d817f1, - 0xb60011cf, - 0x07f10110, - 0x01d005d8, - 0xf104bd00, - 0xf1d900e7, - 0xf5134fe3, - 0xf8022321, -/* 0x0acd: test_init */ - 0x00e7f100, - 0x2321f508, -/* 0x0ad7: idle_recv */ + 0x76bb008a, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb6082421, + 0x11f40464, + 0xe05bcb6a, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0x6921f550, + 0x0464b607, + 0xbd025bb9, + 0x430ef474, +/* 0x0a48: i2c_recv_not_rd08 */ + 0xf401d6b0, + 0x57f03d1b, + 0xd121f500, + 0x3311f408, + 0xf5e0c5c7, + 0xf4087621, + 0x57f02911, + 0xd121f500, + 0x1f11f408, + 0xf5e0b5c7, + 0xf4087621, + 0x21f51511, + 0x74bd0769, + 0xf408c5c7, + 0x32f4091b, + 0x030ef402, +/* 0x0a88: i2c_recv_not_wr08 */ +/* 0x0a88: i2c_recv_done */ + 0xf5f8cec7, + 0xfc093321, + 0xf4d0fce0, + 0x7cb90a12, + 0xe621f502, +/* 0x0a9d: i2c_recv_exit */ +/* 0x0a9f: i2c_init */ 0xf800f802, -/* 0x0ad9: idle */ - 0x0031f400, - 0x05d417f1, - 0xb60011cf, - 0x07f10110, - 0x01d005d4, -/* 0x0aef: idle_loop */ - 0xf004bd00, - 0x32f45817, -/* 0x0af5: idle_proc */ -/* 0x0af5: idle_proc_exec */ - 0xb910f902, - 0x21f5021e, - 0x10fc02fa, - 0xf40911f4, - 0x0ef40231, -/* 0x0b09: idle_proc_next */ - 0x5810b6ef, - 0xf4061fb8, - 0x02f4e61b, - 0x0028f4dd, - 0x00c10ef4, +/* 0x0aa1: test_recv */ + 0xd817f100, + 0x0011cf05, + 0xf10110b6, + 0xd005d807, + 0x04bd0001, + 0xd900e7f1, + 0x134fe3f1, + 0x021821f5, +/* 0x0ac2: test_init */ + 0xe7f100f8, + 0x21f50800, + 0x00f80218, +/* 0x0acc: idle_recv */ +/* 0x0ace: idle */ + 0x31f400f8, + 0xd417f100, + 0x0011cf05, + 0xf10110b6, + 0xd005d407, + 0x04bd0001, +/* 0x0ae4: idle_loop */ + 0xf45817f0, +/* 0x0aea: idle_proc */ +/* 0x0aea: idle_proc_exec */ + 0x10f90232, + 0xf5021eb9, + 0xfc02ef21, + 0x0911f410, + 0xf40231f4, +/* 0x0afe: idle_proc_next */ + 0x10b6ef0e, + 0x061fb858, + 0xf4e61bf4, + 0x28f4dd02, + 0xc10ef400, + 0x00000000, + 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h index fe4f63deeaab..8a2b628642ac 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h @@ -24,8 +24,8 @@ uint32_t gk208_pmu_data[] = { 0x00000000, /* 0x0058: proc_list_head */ 0x54534f48, - 0x00000453, - 0x00000404, + 0x00000447, + 0x000003f8, 0x00000000, 0x00000000, 0x00000000, @@ -46,8 +46,8 @@ uint32_t gk208_pmu_data[] = { 0x00000000, 0x00000000, 0x584d454d, - 0x0000062d, - 0x0000061f, + 0x00000621, + 0x00000613, 0x00000000, 0x00000000, 0x00000000, @@ -68,8 +68,8 @@ uint32_t gk208_pmu_data[] = { 0x00000000, 0x00000000, 0x46524550, - 0x00000631, - 0x0000062f, + 0x00000625, + 0x00000623, 0x00000000, 0x00000000, 0x00000000, @@ -90,8 +90,8 @@ uint32_t gk208_pmu_data[] = { 0x00000000, 0x00000000, 0x5f433249, - 0x00000a35, - 0x000008dc, + 0x00000a29, + 0x000008d0, 0x00000000, 0x00000000, 0x00000000, @@ -112,8 +112,8 @@ uint32_t gk208_pmu_data[] = { 0x00000000, 0x00000000, 0x54534554, - 0x00000a56, - 0x00000a37, + 0x00000a4a, + 0x00000a2b, 0x00000000, 0x00000000, 0x00000000, @@ -134,8 +134,8 @@ uint32_t gk208_pmu_data[] = { 0x00000000, 0x00000000, 0x454c4449, - 0x00000a61, - 0x00000a5f, + 0x00000a55, + 0x00000a53, 0x00000000, 0x00000000, 0x00000000, @@ -229,26 +229,26 @@ uint32_t gk208_pmu_data[] = { /* 0x0370: memx_func_head */ 0x00000001, 0x00000000, - 0x00000483, + 0x00000477, /* 0x037c: memx_func_next */ 0x00000002, 0x00000000, - 0x00000500, + 0x000004f4, 0x00000003, 0x00000002, - 0x00000580, + 0x00000574, 0x00040004, 0x00000000, - 0x0000059d, + 0x00000591, 0x00010005, 0x00000000, - 0x000005b7, + 0x000005ab, 0x00010006, 0x00000000, - 0x0000057b, + 0x0000056f, 0x00000007, 0x00000000, - 0x000005c3, + 0x000005b7, /* 0x03c4: memx_func_tail */ /* 0x03c4: memx_ts_start */ 0x00000000, @@ -916,7 +916,7 @@ uint32_t gk208_pmu_data[] = { }; uint32_t gk208_pmu_code[] = { - 0x031c0ef5, + 0x03100ef5, /* 0x0004: rd32 */ 0xf607a040, 0x04bd000e, @@ -972,7 +972,7 @@ uint32_t gk208_pmu_code[] = { 0x0a98280b, 0x029abb9a, 0x0d0e1cf4, - 0x02617e01, + 0x02557e01, 0xf494bd00, /* 0x00c2: intr_watchdog_next_time */ 0x0a98140e, @@ -1017,21 +1017,16 @@ uint32_t gk208_pmu_code[] = { 0xc0f900cc, 0xf14f484e, 0x0d5453e3, - 0x02c27e00, + 0x02b67e00, 0x40c0fc00, 0x0cf604c0, /* 0x0167: intr_subintr_skip_fifo */ 0x4004bd00, 0x09f60688, /* 0x016f: intr_skip_subintr */ - 0xc404bd00, - 0x0bf42089, - 0xbfa4f107, -/* 0x0179: intr_skip_pause */ - 0x4089c4ff, - 0xf1070bf4, -/* 0x0183: intr_skip_user0 */ - 0x00ffbfa4, + 0x4904bd00, + 0x90bd00e0, + 0x000489fd, 0x0008f604, 0x80fc04bd, 0xfc0088fe, @@ -1040,35 +1035,35 @@ uint32_t gk208_pmu_code[] = { 0xfca0fcb0, 0xfc80fc90, 0x0032f400, -/* 0x01a6: ticks_from_ns */ +/* 0x019a: ticks_from_ns */ 0xc0f901f8, 0xd7f1b0f9, 0xd3f00144, - 0x7721f500, + 0x6b21f500, 0xe8ccec03, 0x00b4b003, 0xec120bf4, 0xf103e8ee, 0xf00144d7, 0x21f500d3, -/* 0x01ce: ticks_from_ns_quit */ - 0xceb20377, +/* 0x01c2: ticks_from_ns_quit */ + 0xceb2036b, 0xc0fcb0fc, -/* 0x01d6: ticks_from_us */ +/* 0x01ca: ticks_from_us */ 0xc0f900f8, 0xd7f1b0f9, 0xd3f00144, - 0x7721f500, + 0x6b21f500, 0xb0ceb203, 0x0bf400b4, -/* 0x01ef: ticks_from_us_quit */ +/* 0x01e3: ticks_from_us_quit */ 0xfce4bd05, 0xf8c0fcb0, -/* 0x01f5: ticks_to_us */ +/* 0x01e9: ticks_to_us */ 0x44d7f100, 0x00d3f001, 0xf8ecedff, -/* 0x0201: timer */ +/* 0x01f5: timer */ 0xf990f900, 0x1032f480, 0xb003f898, @@ -1086,17 +1081,17 @@ uint32_t gk208_pmu_code[] = { 0xa60088cf, 0x080bf4e0, 0x1cf4e8a6, -/* 0x0245: timer_reset */ +/* 0x0239: timer_reset */ 0xf634000d, 0x04bd000e, -/* 0x024f: timer_enable */ +/* 0x0243: timer_enable */ 0x089a0eb5, 0xf6380001, 0x04bd0008, -/* 0x0258: timer_done */ +/* 0x024c: timer_done */ 0xfc1031f4, 0xf890fc80, -/* 0x0261: send_proc */ +/* 0x0255: send_proc */ 0xf980f900, 0x05e89890, 0xf004e998, @@ -1111,24 +1106,24 @@ uint32_t gk208_pmu_code[] = { 0x90b6038b, 0x0794f001, 0xf404e9b5, -/* 0x029a: send_done */ +/* 0x028e: send_done */ 0x90fc0231, 0x00f880fc, -/* 0x02a0: find */ +/* 0x0294: find */ 0x580880f9, -/* 0x02a7: find_loop */ +/* 0x029b: find_loop */ 0x980131f4, 0xaea6008a, 0xb6100bf4, 0x86b15880, 0x1bf40268, 0x0132f4f1, -/* 0x02bc: find_done */ +/* 0x02b0: find_done */ 0x80fc8eb2, -/* 0x02c2: send */ - 0xa07e00f8, +/* 0x02b6: send */ + 0x947e00f8, 0x01f40002, -/* 0x02cb: recv */ +/* 0x02bf: recv */ 0xf900f89b, 0x9880f990, 0xe99805e8, @@ -1148,10 +1143,10 @@ uint32_t gk208_pmu_code[] = { 0xa5f900ee, 0xf8fef0fc, 0x0131f400, -/* 0x0316: recv_done */ +/* 0x030a: recv_done */ 0x80fcf0fc, 0x00f890fc, -/* 0x031c: init */ +/* 0x0310: init */ 0xcf010841, 0x11e70011, 0x14b60109, @@ -1170,12 +1165,12 @@ uint32_t gk208_pmu_code[] = { 0x011031f4, 0xf6380001, 0x04bd0001, -/* 0x0366: init_proc */ +/* 0x035a: init_proc */ 0xf198580f, 0x0016b001, 0xf9fa0bf4, 0x58f0b615, -/* 0x0377: mulu32_32_64 */ +/* 0x036b: mulu32_32_64 */ 0xf9f20ef4, 0xf920f910, 0x9540f930, @@ -1196,7 +1191,7 @@ uint32_t gk208_pmu_code[] = { 0x00b3bb30, 0x30fc40fc, 0x10fc20fc, -/* 0x03c6: host_send */ +/* 0x03ba: host_send */ 0xb04100f8, 0x0011cf04, 0xcf04a042, @@ -1207,18 +1202,18 @@ uint32_t gk208_pmu_code[] = { 0x03eb9802, 0x9802ec98, 0xee9801ed, - 0x02c27e00, + 0x02b67e00, 0x0110b600, 0x400f1ec4, 0x0ef604b0, 0xf404bd00, -/* 0x0402: host_send_done */ +/* 0x03f6: host_send_done */ 0x00f8c70e, -/* 0x0404: host_recv */ +/* 0x03f8: host_recv */ 0xf14e4941, 0xa6525413, 0xb90bf4e1, -/* 0x0410: host_recv_wait */ +/* 0x0404: host_recv_wait */ 0xcf04cc41, 0xc8420011, 0x0022cf04, @@ -1235,7 +1230,7 @@ uint32_t gk208_pmu_code[] = { 0x04bd0002, 0x00004002, 0xbd0002f6, -/* 0x0453: host_init */ +/* 0x0447: host_init */ 0x4100f804, 0x14b60080, 0x7015f110, @@ -1248,7 +1243,7 @@ uint32_t gk208_pmu_code[] = { 0x0104bd00, 0x04c44001, 0xbd0001f6, -/* 0x0483: memx_func_enter */ +/* 0x0477: memx_func_enter */ 0xf100f804, 0xf1162067, 0xf1f55d77, @@ -1275,19 +1270,19 @@ uint32_t gk208_pmu_code[] = { 0x00002e7e, 0xe0400406, 0x0006f607, -/* 0x04ea: memx_func_enter_wait */ +/* 0x04de: memx_func_enter_wait */ 0xc04604bd, 0x0066cf07, 0xf40464f0, 0x2c06f70b, 0xb50066cf, 0x00f8f106, -/* 0x0500: memx_func_leave */ +/* 0x04f4: memx_func_leave */ 0x66cf2c06, 0xf206b500, 0xe4400406, 0x0006f607, -/* 0x0512: memx_func_leave_wait */ +/* 0x0506: memx_func_leave_wait */ 0xc04604bd, 0x0066cf07, 0xf40464f0, @@ -1314,10 +1309,10 @@ uint32_t gk208_pmu_code[] = { 0xf960f905, 0xfcd0fc80, 0x002e7ee0, -/* 0x057b: memx_func_wait_vblank */ +/* 0x056f: memx_func_wait_vblank */ 0xb600f800, 0x00f80410, -/* 0x0580: memx_func_wr32 */ +/* 0x0574: memx_func_wr32 */ 0x98001698, 0x10b60115, 0xf960f908, @@ -1325,23 +1320,23 @@ uint32_t gk208_pmu_code[] = { 0x002e7ee0, 0x0242b600, 0xf8e81bf4, -/* 0x059d: memx_func_wait */ +/* 0x0591: memx_func_wait */ 0xcf2c0800, 0x1e980088, 0x011d9800, 0x98021c98, 0x10b6031b, 0x00797e10, -/* 0x05b7: memx_func_delay */ +/* 0x05ab: memx_func_delay */ 0x9800f800, 0x10b6001e, 0x005d7e04, -/* 0x05c3: memx_func_train */ +/* 0x05b7: memx_func_train */ 0xf800f800, -/* 0x05c5: memx_exec */ +/* 0x05b9: memx_exec */ 0xf9e0f900, 0xb2c1b2d0, -/* 0x05cd: memx_exec_next */ +/* 0x05c1: memx_exec_next */ 0x001398b2, 0xe70410b6, 0xe701f034, @@ -1354,111 +1349,111 @@ uint32_t gk208_pmu_code[] = { 0x02cbbbf2, 0xcf07c44b, 0xd0fc00bb, - 0xc27ee0fc, + 0xb67ee0fc, 0x00f80002, -/* 0x0604: memx_info */ +/* 0x05f8: memx_info */ 0xf401c670, -/* 0x060a: memx_info_data */ +/* 0x05fe: memx_info_data */ 0xcc4c0c0b, 0x08004b03, -/* 0x0613: memx_info_train */ +/* 0x0607: memx_info_train */ 0x4c090ef4, 0x004b0bcc, -/* 0x0619: memx_info_send */ - 0x02c27e01, -/* 0x061f: memx_recv */ +/* 0x060d: memx_info_send */ + 0x02b67e01, +/* 0x0613: memx_recv */ 0xb000f800, 0x0bf401d6, 0x00d6b0a3, 0xf8dc0bf4, -/* 0x062d: memx_init */ -/* 0x062f: perf_recv */ +/* 0x0621: memx_init */ +/* 0x0623: perf_recv */ 0xf800f800, -/* 0x0631: perf_init */ -/* 0x0633: i2c_drive_scl */ +/* 0x0625: perf_init */ +/* 0x0627: i2c_drive_scl */ 0xb000f800, 0x0bf40036, 0x07e0400d, 0xbd0001f6, -/* 0x0643: i2c_drive_scl_lo */ +/* 0x0637: i2c_drive_scl_lo */ 0x4000f804, 0x01f607e4, 0xf804bd00, -/* 0x064d: i2c_drive_sda */ +/* 0x0641: i2c_drive_sda */ 0x0036b000, 0x400d0bf4, 0x02f607e0, 0xf804bd00, -/* 0x065d: i2c_drive_sda_lo */ +/* 0x0651: i2c_drive_sda_lo */ 0x07e44000, 0xbd0002f6, -/* 0x0667: i2c_sense_scl */ +/* 0x065b: i2c_sense_scl */ 0xf400f804, 0xc4430132, 0x0033cf07, 0xf40431fd, 0x31f4060b, -/* 0x0679: i2c_sense_scl_done */ -/* 0x067b: i2c_sense_sda */ +/* 0x066d: i2c_sense_scl_done */ +/* 0x066f: i2c_sense_sda */ 0xf400f801, 0xc4430132, 0x0033cf07, 0xf40432fd, 0x31f4060b, -/* 0x068d: i2c_sense_sda_done */ -/* 0x068f: i2c_raise_scl */ +/* 0x0681: i2c_sense_sda_done */ +/* 0x0683: i2c_raise_scl */ 0xf900f801, 0x08984440, - 0x337e0103, -/* 0x069a: i2c_raise_scl_wait */ + 0x277e0103, +/* 0x068e: i2c_raise_scl_wait */ 0xe84e0006, 0x005d7e03, - 0x06677e00, + 0x065b7e00, 0x0901f400, 0xf40142b6, -/* 0x06ae: i2c_raise_scl_done */ +/* 0x06a2: i2c_raise_scl_done */ 0x40fcef1b, -/* 0x06b2: i2c_start */ - 0x677e00f8, +/* 0x06a6: i2c_start */ + 0x5b7e00f8, 0x11f40006, - 0x067b7e0d, + 0x066f7e0d, 0x0611f400, -/* 0x06c3: i2c_start_rep */ +/* 0x06b7: i2c_start_rep */ 0x032e0ef4, - 0x06337e00, + 0x06277e00, 0x7e010300, - 0xbb00064d, + 0xbb000641, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x00068f7e, + 0x0006837e, 0xf40464b6, -/* 0x06ee: i2c_start_send */ +/* 0x06e2: i2c_start_send */ 0x00031d11, - 0x00064d7e, + 0x0006417e, 0x7e13884e, 0x0300005d, - 0x06337e00, + 0x06277e00, 0x13884e00, 0x00005d7e, -/* 0x0708: i2c_start_out */ -/* 0x070a: i2c_stop */ +/* 0x06fc: i2c_start_out */ +/* 0x06fe: i2c_stop */ 0x000300f8, - 0x0006337e, - 0x4d7e0003, + 0x0006277e, + 0x417e0003, 0xe84e0006, 0x005d7e03, 0x7e010300, - 0x4e000633, + 0x4e000627, 0x5d7e1388, 0x01030000, - 0x00064d7e, + 0x0006417e, 0x7e13884e, 0xf800005d, -/* 0x0739: i2c_bitw */ - 0x064d7e00, +/* 0x072d: i2c_bitw */ + 0x06417e00, 0x03e84e00, 0x00005d7e, 0xb60076bb, @@ -1466,18 +1461,18 @@ uint32_t gk208_pmu_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x068f7e50, + 0x06837e50, 0x0464b600, 0x4e1711f4, 0x5d7e1388, 0x00030000, - 0x0006337e, + 0x0006277e, 0x7e13884e, -/* 0x0777: i2c_bitw_out */ +/* 0x076b: i2c_bitw_out */ 0xf800005d, -/* 0x0779: i2c_bitr */ +/* 0x076d: i2c_bitr */ 0x7e010300, - 0x4e00064d, + 0x4e000641, 0x5d7e03e8, 0x76bb0000, 0x0465b600, @@ -1485,25 +1480,25 @@ uint32_t gk208_pmu_code[] = { 0x0256bb04, 0x75fd50bd, 0x7e50fc04, - 0xb600068f, + 0xb6000683, 0x11f40464, - 0x067b7e1a, + 0x066f7e1a, 0x7e000300, - 0x4e000633, + 0x4e000627, 0x5d7e1388, 0x3cf00000, 0x0131f401, -/* 0x07bc: i2c_bitr_done */ -/* 0x07be: i2c_get_byte */ +/* 0x07b0: i2c_bitr_done */ +/* 0x07b2: i2c_get_byte */ 0x000500f8, -/* 0x07c2: i2c_get_byte_next */ +/* 0x07b6: i2c_get_byte_next */ 0x54b60804, 0x0076bb01, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, - 0x797e50fc, + 0x6d7e50fc, 0x64b60007, 0x2a11f404, 0xb60553fd, @@ -1514,11 +1509,11 @@ uint32_t gk208_pmu_code[] = { 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x0007397e, -/* 0x080b: i2c_get_byte_done */ + 0x00072d7e, +/* 0x07ff: i2c_get_byte_done */ 0xf80464b6, -/* 0x080d: i2c_put_byte */ -/* 0x080f: i2c_put_byte_next */ +/* 0x0801: i2c_put_byte */ +/* 0x0803: i2c_put_byte_next */ 0xb6080400, 0x54ff0142, 0x0076bb38, @@ -1526,7 +1521,7 @@ uint32_t gk208_pmu_code[] = { 0x04659450, 0xbd0256bb, 0x0475fd50, - 0x397e50fc, + 0x2d7e50fc, 0x64b60007, 0x3411f404, 0xf40046b0, @@ -1536,20 +1531,20 @@ uint32_t gk208_pmu_code[] = { 0x0256bb04, 0x75fd50bd, 0x7e50fc04, - 0xb6000779, + 0xb600076d, 0x11f40464, 0x0076bb0f, 0xf40136b0, 0x32f4061b, -/* 0x0865: i2c_put_byte_done */ -/* 0x0867: i2c_addr */ +/* 0x0859: i2c_put_byte_done */ +/* 0x085b: i2c_addr */ 0xbb00f801, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x0006b27e, + 0x0006a67e, 0xf40464b6, 0xc3e72911, 0x34b6012e, @@ -1559,25 +1554,25 @@ uint32_t gk208_pmu_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x080d7e50, + 0x08017e50, 0x0464b600, -/* 0x08ac: i2c_addr_done */ -/* 0x08ae: i2c_acquire_addr */ +/* 0x08a0: i2c_addr_done */ +/* 0x08a2: i2c_acquire_addr */ 0xcec700f8, 0x05e4b6f8, 0xd014e0b7, -/* 0x08ba: i2c_acquire */ - 0xae7e00f8, +/* 0x08ae: i2c_acquire */ + 0xa27e00f8, 0x047e0008, 0xd9f00000, 0x002e7e03, -/* 0x08cb: i2c_release */ +/* 0x08bf: i2c_release */ 0x7e00f800, - 0x7e0008ae, + 0x7e0008a2, 0xf0000004, 0x2e7e03da, 0x00f80000, -/* 0x08dc: i2c_recv */ +/* 0x08d0: i2c_recv */ 0xc70132f4, 0x14b6f8c1, 0x2816b002, @@ -1596,7 +1591,7 @@ uint32_t gk208_pmu_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x08ba7e50, + 0x08ae7e50, 0x0464b600, 0xd6b0d0fc, 0xb01bf500, @@ -1606,7 +1601,7 @@ uint32_t gk208_pmu_code[] = { 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x0008677e, + 0x00085b7e, 0xf50464b6, 0xc700cc11, 0x76bbe0c5, @@ -1615,7 +1610,7 @@ uint32_t gk208_pmu_code[] = { 0x0256bb04, 0x75fd50bd, 0x7e50fc04, - 0xb600080d, + 0xb6000801, 0x11f50464, 0x010500a9, 0xb60076bb, @@ -1623,7 +1618,7 @@ uint32_t gk208_pmu_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x08677e50, + 0x085b7e50, 0x0464b600, 0x008711f5, 0xb60076bb, @@ -1631,7 +1626,7 @@ uint32_t gk208_pmu_code[] = { 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0x07be7e50, + 0x07b27e50, 0x0464b600, 0xcb6711f4, 0x76bbe05b, @@ -1640,36 +1635,36 @@ uint32_t gk208_pmu_code[] = { 0x0256bb04, 0x75fd50bd, 0x7e50fc04, - 0xb600070a, + 0xb60006fe, 0x5bb20464, 0x0ef474bd, -/* 0x09e1: i2c_recv_not_rd08 */ +/* 0x09d5: i2c_recv_not_rd08 */ 0x01d6b041, 0x053b1bf4, - 0x08677e00, + 0x085b7e00, 0x3211f400, 0x7ee0c5c7, - 0xf400080d, + 0xf4000801, 0x00052811, - 0x0008677e, + 0x00085b7e, 0xc71f11f4, - 0x0d7ee0b5, + 0x017ee0b5, 0x11f40008, - 0x070a7e15, + 0x06fe7e15, 0xc774bd00, 0x1bf408c5, 0x0232f409, -/* 0x0a1f: i2c_recv_not_wr08 */ -/* 0x0a1f: i2c_recv_done */ +/* 0x0a13: i2c_recv_not_wr08 */ +/* 0x0a13: i2c_recv_done */ 0xc7030ef4, - 0xcb7ef8ce, + 0xbf7ef8ce, 0xe0fc0008, 0x12f4d0fc, 0x7e7cb209, -/* 0x0a33: i2c_recv_exit */ - 0xf80002c2, -/* 0x0a35: i2c_init */ -/* 0x0a37: test_recv */ +/* 0x0a27: i2c_recv_exit */ + 0xf80002b6, +/* 0x0a29: i2c_init */ +/* 0x0a2b: test_recv */ 0x4100f800, 0x11cf0458, 0x0110b600, @@ -1677,28 +1672,28 @@ uint32_t gk208_pmu_code[] = { 0x04bd0001, 0xd900e7f1, 0x134fe3f1, - 0x0002017e, -/* 0x0a56: test_init */ + 0x0001f57e, +/* 0x0a4a: test_init */ 0x004e00f8, - 0x02017e08, -/* 0x0a5f: idle_recv */ + 0x01f57e08, +/* 0x0a53: idle_recv */ 0xf800f800, -/* 0x0a61: idle */ +/* 0x0a55: idle */ 0x0031f400, 0xcf045441, 0x10b60011, 0x04544001, 0xbd0001f6, -/* 0x0a75: idle_loop */ +/* 0x0a69: idle_loop */ 0xf4580104, -/* 0x0a7a: idle_proc */ -/* 0x0a7a: idle_proc_exec */ +/* 0x0a6e: idle_proc */ +/* 0x0a6e: idle_proc_exec */ 0x10f90232, - 0xcb7e1eb2, + 0xbf7e1eb2, 0x10fc0002, 0xf40911f4, 0x0ef40231, -/* 0x0a8d: idle_proc_next */ +/* 0x0a81: idle_proc_next */ 0x5810b6f0, 0x1bf41fa6, 0xe002f4e8, @@ -1728,4 +1723,7 @@ uint32_t gk208_pmu_code[] = { 0x00000000, 0x00000000, 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h index 2686f8fad0f5..516569270bac 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h @@ -24,8 +24,8 @@ uint32_t gt215_pmu_data[] = { 0x00000000, /* 0x0058: proc_list_head */ 0x54534f48, - 0x00000512, - 0x000004af, + 0x00000507, + 0x000004a4, 0x00000000, 0x00000000, 0x00000000, @@ -46,8 +46,8 @@ uint32_t gt215_pmu_data[] = { 0x00000000, 0x00000000, 0x584d454d, - 0x00000842, - 0x00000834, + 0x00000837, + 0x00000829, 0x00000000, 0x00000000, 0x00000000, @@ -68,8 +68,8 @@ uint32_t gt215_pmu_data[] = { 0x00000000, 0x00000000, 0x46524550, - 0x00000846, - 0x00000844, + 0x0000083b, + 0x00000839, 0x00000000, 0x00000000, 0x00000000, @@ -90,8 +90,8 @@ uint32_t gt215_pmu_data[] = { 0x00000000, 0x00000000, 0x5f433249, - 0x00000c76, - 0x00000b19, + 0x00000c6b, + 0x00000b0e, 0x00000000, 0x00000000, 0x00000000, @@ -112,8 +112,8 @@ uint32_t gt215_pmu_data[] = { 0x00000000, 0x00000000, 0x54534554, - 0x00000c9f, - 0x00000c78, + 0x00000c94, + 0x00000c6d, 0x00000000, 0x00000000, 0x00000000, @@ -134,8 +134,8 @@ uint32_t gt215_pmu_data[] = { 0x00000000, 0x00000000, 0x454c4449, - 0x00000cab, - 0x00000ca9, + 0x00000ca0, + 0x00000c9e, 0x00000000, 0x00000000, 0x00000000, @@ -229,26 +229,26 @@ uint32_t gt215_pmu_data[] = { /* 0x0370: memx_func_head */ 0x00000001, 0x00000000, - 0x00000551, + 0x00000546, /* 0x037c: memx_func_next */ 0x00000002, 0x00000000, - 0x000005a8, + 0x0000059d, 0x00000003, 0x00000002, - 0x0000063a, + 0x0000062f, 0x00040004, 0x00000000, - 0x00000656, + 0x0000064b, 0x00010005, 0x00000000, - 0x00000673, + 0x00000668, 0x00010006, 0x00000000, - 0x000005f8, + 0x000005ed, 0x00000007, 0x00000000, - 0x0000067e, + 0x00000673, /* 0x03c4: memx_func_tail */ /* 0x03c4: memx_ts_start */ 0x00000000, @@ -917,7 +917,7 @@ uint32_t gt215_pmu_data[] = { }; uint32_t gt215_pmu_code[] = { - 0x039e0ef5, + 0x03930ef5, /* 0x0004: rd32 */ 0x07a007f1, 0xd00604b6, @@ -987,7 +987,7 @@ uint32_t gt215_pmu_code[] = { 0xbb9a0a98, 0x1cf4029a, 0x01d7f00f, - 0x02dd21f5, + 0x02d221f5, 0x0ef494bd, /* 0x00f9: intr_watchdog_next_time */ 0x9b0a9815, @@ -1039,7 +1039,7 @@ uint32_t gt215_pmu_code[] = { 0x48e7f1c0, 0x53e3f14f, 0x00d7f054, - 0x034221f5, + 0x033721f5, 0x07f1c0fc, 0x04b604c0, 0x000cd006, @@ -1048,820 +1048,818 @@ uint32_t gt215_pmu_code[] = { 0x04b60688, 0x0009d006, /* 0x01ca: intr_skip_subintr */ - 0x89c404bd, - 0x070bf420, - 0xffbfa4f1, -/* 0x01d4: intr_skip_pause */ - 0xf44089c4, - 0xa4f1070b, -/* 0x01de: intr_skip_user0 */ - 0x07f0ffbf, - 0x0604b604, - 0xbd0008d0, - 0xfe80fc04, - 0xf0fc0088, - 0xd0fce0fc, - 0xb0fcc0fc, - 0x90fca0fc, - 0x00fc80fc, - 0xf80032f4, -/* 0x0205: ticks_from_ns */ - 0xf9c0f901, - 0xcbd7f1b0, - 0x00d3f000, - 0x041321f5, - 0x03e8ccec, - 0xf400b4b0, - 0xeeec120b, - 0xd7f103e8, - 0xd3f000cb, - 0x1321f500, -/* 0x022d: ticks_from_ns_quit */ - 0x02ceb904, - 0xc0fcb0fc, -/* 0x0236: ticks_from_us */ - 0xc0f900f8, + 0x97f104bd, + 0x90bd00e0, + 0xf00489fd, + 0x04b60407, + 0x0008d006, + 0x80fc04bd, + 0xfc0088fe, + 0xfce0fcf0, + 0xfcc0fcd0, + 0xfca0fcb0, + 0xfc80fc90, + 0x0032f400, +/* 0x01fa: ticks_from_ns */ + 0xc0f901f8, 0xd7f1b0f9, 0xd3f000cb, - 0x1321f500, - 0x02ceb904, - 0xf400b4b0, - 0xe4bd050b, -/* 0x0250: ticks_from_us_quit */ - 0xc0fcb0fc, -/* 0x0256: ticks_to_us */ - 0xd7f100f8, - 0xd3f000cb, - 0xecedff00, -/* 0x0262: timer */ - 0x90f900f8, - 0x32f480f9, - 0x03f89810, - 0xf40086b0, - 0x84bd651c, - 0xb63807f0, - 0x08d00604, - 0xf004bd00, - 0x84b63487, - 0x0088cf06, - 0xbb9a0998, - 0xe9bb0298, - 0x03fe8000, - 0xb60887f0, - 0x88cf0684, - 0x0284f000, - 0xf0261bf4, - 0x84b63487, - 0x0088cf06, - 0xf406e0b8, - 0xe8b8090b, - 0x111cf406, -/* 0x02b8: timer_reset */ - 0xb63407f0, - 0x0ed00604, - 0x8004bd00, -/* 0x02c6: timer_enable */ - 0x87f09a0e, - 0x3807f001, + 0x0821f500, + 0xe8ccec04, + 0x00b4b003, + 0xec120bf4, + 0xf103e8ee, + 0xf000cbd7, + 0x21f500d3, +/* 0x0222: ticks_from_ns_quit */ + 0xceb90408, + 0xfcb0fc02, +/* 0x022b: ticks_from_us */ + 0xf900f8c0, + 0xf1b0f9c0, + 0xf000cbd7, + 0x21f500d3, + 0xceb90408, + 0x00b4b002, + 0xbd050bf4, +/* 0x0245: ticks_from_us_quit */ + 0xfcb0fce4, +/* 0x024b: ticks_to_us */ + 0xf100f8c0, + 0xf000cbd7, + 0xedff00d3, +/* 0x0257: timer */ + 0xf900f8ec, + 0xf480f990, + 0xf8981032, + 0x0086b003, + 0xbd651cf4, + 0x3807f084, 0xd00604b6, 0x04bd0008, -/* 0x02d4: timer_done */ - 0xfc1031f4, - 0xf890fc80, -/* 0x02dd: send_proc */ - 0xf980f900, - 0x05e89890, - 0xf004e998, - 0x89b80486, - 0x2a0bf406, - 0x940398c4, - 0x80b60488, - 0x008ebb18, - 0x8000fa98, - 0x8d80008a, - 0x028c8001, - 0xb6038b80, - 0x94f00190, - 0x04e98007, -/* 0x0317: send_done */ - 0xfc0231f4, - 0xf880fc90, -/* 0x031d: find */ - 0xf080f900, - 0x31f45887, -/* 0x0325: find_loop */ - 0x008a9801, - 0xf406aeb8, - 0x80b6100b, - 0x6886b158, - 0xf01bf402, -/* 0x033b: find_done */ - 0xb90132f4, - 0x80fc028e, -/* 0x0342: send */ - 0x21f500f8, - 0x01f4031d, -/* 0x034b: recv */ - 0xf900f897, - 0x9880f990, - 0xe99805e8, - 0x0132f404, - 0xf40689b8, - 0x89c43d0b, - 0x0180b603, - 0x800784f0, - 0xea9805e8, - 0xfef0f902, - 0xf0f9018f, - 0x9402efb9, - 0xe9bb0499, - 0x18e0b600, - 0x9803eb98, - 0xed9802ec, - 0x00ee9801, - 0xf0fca5f9, - 0xf400f8fe, - 0xf0fc0131, -/* 0x0398: recv_done */ - 0x90fc80fc, -/* 0x039e: init */ - 0x17f100f8, - 0x14b60108, - 0x0011cf06, - 0x010911e7, - 0xfe0814b6, - 0x17f10014, - 0x13f000e0, - 0x1c07f000, - 0xd00604b6, - 0x04bd0001, - 0xf0ff17f0, - 0x04b61407, - 0x0001d006, - 0x17f004bd, - 0x0015f102, - 0x1007f008, + 0xb63487f0, + 0x88cf0684, + 0x9a099800, + 0xbb0298bb, + 0xfe8000e9, + 0x0887f003, + 0xcf0684b6, + 0x84f00088, + 0x261bf402, + 0xb63487f0, + 0x88cf0684, + 0x06e0b800, + 0xb8090bf4, + 0x1cf406e8, +/* 0x02ad: timer_reset */ + 0x3407f011, 0xd00604b6, - 0x04bd0001, - 0x011a17f1, - 0xfe0013f0, - 0x31f40010, - 0x0117f010, - 0xb63807f0, + 0x04bd000e, +/* 0x02bb: timer_enable */ + 0xf09a0e80, + 0x07f00187, + 0x0604b638, + 0xbd0008d0, +/* 0x02c9: timer_done */ + 0x1031f404, + 0x90fc80fc, +/* 0x02d2: send_proc */ + 0x80f900f8, + 0xe89890f9, + 0x04e99805, + 0xb80486f0, + 0x0bf40689, + 0x0398c42a, + 0xb6048894, + 0x8ebb1880, + 0x00fa9800, + 0x80008a80, + 0x8c80018d, + 0x038b8002, + 0xf00190b6, + 0xe9800794, + 0x0231f404, +/* 0x030c: send_done */ + 0x80fc90fc, +/* 0x0312: find */ + 0x80f900f8, + 0xf45887f0, +/* 0x031a: find_loop */ + 0x8a980131, + 0x06aeb800, + 0xb6100bf4, + 0x86b15880, + 0x1bf40268, + 0x0132f4f0, +/* 0x0330: find_done */ + 0xfc028eb9, +/* 0x0337: send */ + 0xf500f880, + 0xf4031221, + 0x00f89701, +/* 0x0340: recv */ + 0x80f990f9, + 0x9805e898, + 0x32f404e9, + 0x0689b801, + 0xc43d0bf4, + 0x80b60389, + 0x0784f001, + 0x9805e880, + 0xf0f902ea, + 0xf9018ffe, + 0x02efb9f0, + 0xbb049994, + 0xe0b600e9, + 0x03eb9818, + 0x9802ec98, + 0xee9801ed, + 0xfca5f900, + 0x00f8fef0, + 0xfc0131f4, +/* 0x038d: recv_done */ + 0xfc80fcf0, +/* 0x0393: init */ + 0xf100f890, + 0xb6010817, + 0x11cf0614, + 0x0911e700, + 0x0814b601, + 0xf10014fe, + 0xf000e017, + 0x07f00013, + 0x0604b61c, + 0xbd0001d0, + 0xff17f004, + 0xb61407f0, 0x01d00604, 0xf004bd00, -/* 0x0402: init_proc */ - 0xf19858f7, - 0x0016b001, - 0xf9fa0bf4, - 0x58f0b615, -/* 0x0413: mulu32_32_64 */ - 0xf9f20ef4, - 0xf920f910, - 0x9540f930, - 0xd29510e1, - 0xbdc4bd10, - 0xc0edffb4, - 0xb9301dff, - 0x34f10234, - 0x34b6ffff, - 0x1045b610, - 0xbb00c3bb, - 0xe2ff01b4, - 0x0234b930, - 0xffff34f1, - 0xb61034b6, - 0xc3bb1045, - 0x01b4bb00, - 0xbb3012ff, - 0x40fc00b3, - 0x20fc30fc, - 0x00f810fc, -/* 0x0464: host_send */ - 0x04b017f1, - 0xcf0614b6, - 0x27f10011, - 0x24b604a0, - 0x0022cf06, - 0xf40612b8, - 0x1ec4320b, - 0x04ee9407, - 0x0270e0b7, - 0x9803eb98, - 0xed9802ec, - 0x00ee9801, - 0x034221f5, - 0xc40110b6, - 0x07f10f1e, - 0x04b604b0, - 0x000ed006, - 0x0ef404bd, -/* 0x04ad: host_send_done */ -/* 0x04af: host_recv */ - 0xf100f8ba, - 0xf14e4917, - 0xb8525413, - 0x0bf406e1, -/* 0x04bd: host_recv_wait */ - 0xcc17f1aa, + 0x15f10217, + 0x07f00800, + 0x0604b610, + 0xbd0001d0, + 0x1a17f104, + 0x0013f001, + 0xf40010fe, + 0x17f01031, + 0x3807f001, + 0xd00604b6, + 0x04bd0001, +/* 0x03f7: init_proc */ + 0x9858f7f0, + 0x16b001f1, + 0xfa0bf400, + 0xf0b615f9, + 0xf20ef458, +/* 0x0408: mulu32_32_64 */ + 0x20f910f9, + 0x40f930f9, + 0x9510e195, + 0xc4bd10d2, + 0xedffb4bd, + 0x301dffc0, + 0xf10234b9, + 0xb6ffff34, + 0x45b61034, + 0x00c3bb10, + 0xff01b4bb, + 0x34b930e2, + 0xff34f102, + 0x1034b6ff, + 0xbb1045b6, + 0xb4bb00c3, + 0x3012ff01, + 0xfc00b3bb, + 0xfc30fc40, + 0xf810fc20, +/* 0x0459: host_send */ + 0xb017f100, 0x0614b604, 0xf10011cf, - 0xb604c827, + 0xb604a027, 0x22cf0624, - 0x0816f000, - 0xf40612b8, - 0x23c4e60b, - 0x0434b607, - 0x02f030b7, - 0x80033b80, - 0x3d80023c, - 0x003e8001, - 0xf00120b6, - 0x07f10f24, - 0x04b604c8, - 0x0002d006, - 0x27f004bd, - 0x0007f040, - 0xd00604b6, - 0x04bd0002, -/* 0x0512: host_init */ - 0x17f100f8, + 0x0612b800, + 0xc4320bf4, + 0xee94071e, + 0x70e0b704, + 0x03eb9802, + 0x9802ec98, + 0xee9801ed, + 0x3721f500, + 0x0110b603, + 0xf10f1ec4, + 0xb604b007, + 0x0ed00604, + 0xf404bd00, +/* 0x04a2: host_send_done */ + 0x00f8ba0e, +/* 0x04a4: host_recv */ + 0x4e4917f1, + 0x525413f1, + 0xf406e1b8, +/* 0x04b2: host_recv_wait */ + 0x17f1aa0b, + 0x14b604cc, + 0x0011cf06, + 0x04c827f1, + 0xcf0624b6, + 0x16f00022, + 0x0612b808, + 0xc4e60bf4, + 0x34b60723, + 0xf030b704, + 0x033b8002, + 0x80023c80, + 0x3e80013d, + 0x0120b600, + 0xf10f24f0, + 0xb604c807, + 0x02d00604, + 0xf004bd00, + 0x07f04027, + 0x0604b600, + 0xbd0002d0, +/* 0x0507: host_init */ + 0xf100f804, + 0xb6008017, + 0x15f11014, + 0x07f10270, + 0x04b604d0, + 0x0001d006, + 0x17f104bd, 0x14b60080, - 0x7015f110, - 0xd007f102, + 0xf015f110, + 0xdc07f102, 0x0604b604, 0xbd0001d0, - 0x8017f104, - 0x1014b600, - 0x02f015f1, - 0x04dc07f1, + 0x0117f004, + 0x04c407f1, 0xd00604b6, 0x04bd0001, - 0xf10117f0, - 0xb604c407, - 0x01d00604, - 0xf804bd00, -/* 0x0551: memx_func_enter */ - 0x1087f100, - 0x028eb916, - 0xb90421f4, - 0x67f102d7, - 0x63f1fffc, - 0x76fdffff, - 0x0267f104, - 0x0576fd00, - 0x70f980f9, - 0xe0fcd0fc, - 0xf03f21f4, - 0x07f10467, - 0x04b607e0, - 0x0006d006, -/* 0x058a: memx_func_enter_wait */ - 0x67f104bd, - 0x64b607c0, - 0x0066cf06, - 0xf40464f0, - 0x67f0f30b, - 0x0664b62c, - 0x800066cf, - 0x00f8f106, -/* 0x05a8: memx_func_leave */ - 0xb62c67f0, - 0x66cf0664, - 0xf2068000, +/* 0x0546: memx_func_enter */ + 0x87f100f8, + 0x8eb91610, + 0x0421f402, + 0xf102d7b9, + 0xf1fffc67, + 0xfdffff63, + 0x67f10476, + 0x76fd0002, + 0xf980f905, + 0xfcd0fc70, + 0x3f21f4e0, 0xf10467f0, - 0xb607e407, + 0xb607e007, 0x06d00604, -/* 0x05c3: memx_func_leave_wait */ +/* 0x057f: memx_func_enter_wait */ 0xf104bd00, 0xb607c067, 0x66cf0664, 0x0464f000, - 0xf1f31bf4, - 0xb9161087, - 0x21f4028e, - 0x02d7b904, - 0xffcc67f1, - 0xffff63f1, - 0xf90476fd, - 0xfc70f980, - 0xf4e0fcd0, - 0x00f83f21, -/* 0x05f8: memx_func_wait_vblank */ - 0xb0001698, - 0x0bf40066, - 0x0166b013, - 0xf4060bf4, -/* 0x060a: memx_func_wait_vblank_head1 */ - 0x77f12e0e, - 0x0ef40020, -/* 0x0611: memx_func_wait_vblank_head0 */ - 0x0877f107, -/* 0x0615: memx_func_wait_vblank_0 */ - 0xc467f100, - 0x0664b607, - 0xfd0066cf, - 0x1bf40467, -/* 0x0625: memx_func_wait_vblank_1 */ - 0xc467f1f3, - 0x0664b607, - 0xfd0066cf, - 0x0bf40467, -/* 0x0635: memx_func_wait_vblank_fini */ - 0x0410b6f3, -/* 0x063a: memx_func_wr32 */ - 0x169800f8, - 0x01159800, - 0xf90810b6, - 0xfc50f960, - 0xf4e0fcd0, - 0x42b63f21, - 0xe91bf402, -/* 0x0656: memx_func_wait */ - 0x87f000f8, - 0x0684b62c, - 0x980088cf, - 0x1d98001e, - 0x021c9801, - 0xb6031b98, - 0x21f41010, -/* 0x0673: memx_func_delay */ - 0x9800f8a4, - 0x10b6001e, - 0x7f21f404, -/* 0x067e: memx_func_train */ - 0x57f100f8, - 0x77f10003, - 0x97f10000, - 0x93f00000, - 0x029eb970, - 0xb90421f4, - 0xe7f102d8, - 0x21f42710, -/* 0x069d: memx_func_train_loop_outer */ - 0x0158e07f, - 0x0083f101, - 0xe097f102, - 0x1193f011, - 0x80f990f9, + 0xf0f30bf4, + 0x64b62c67, + 0x0066cf06, + 0xf8f10680, +/* 0x059d: memx_func_leave */ + 0x2c67f000, + 0xcf0664b6, + 0x06800066, + 0x0467f0f2, + 0x07e407f1, + 0xd00604b6, + 0x04bd0006, +/* 0x05b8: memx_func_leave_wait */ + 0x07c067f1, + 0xcf0664b6, + 0x64f00066, + 0xf31bf404, + 0x161087f1, + 0xf4028eb9, + 0xd7b90421, + 0xcc67f102, + 0xff63f1ff, + 0x0476fdff, + 0x70f980f9, 0xe0fcd0fc, - 0xf93f21f4, - 0x0067f150, -/* 0x06bd: memx_func_train_loop_inner */ - 0x1187f100, - 0x9068ff11, - 0xfd109894, - 0x97f10589, - 0x93f00720, - 0xf990f910, - 0xfcd0fc80, - 0x3f21f4e0, - 0x008097f1, - 0xb91093f0, - 0x21f4029e, - 0x02d8b904, - 0xf92088c5, - 0xfc80f990, - 0xf4e0fcd0, - 0x97f13f21, - 0x93f0053c, - 0x0287f110, - 0x0083f130, - 0xf990f980, - 0xfcd0fc80, - 0x3f21f4e0, - 0x0560e7f1, - 0xf110e3f0, - 0xf10000d7, - 0x908000d3, - 0xb7f100dc, - 0xb3f08480, - 0xa421f41e, - 0x000057f1, - 0xffff97f1, - 0x830093f1, -/* 0x073c: memx_func_train_loop_4x */ - 0x0080a7f1, - 0xb910a3f0, - 0x21f402ae, - 0x02d8b904, - 0xffdfb7f1, - 0xffffb3f1, - 0xf9048bfd, - 0xfc80f9a0, - 0xf4e0fcd0, - 0xa7f13f21, - 0xa3f0053c, - 0x0287f110, - 0x0083f130, - 0xf9a0f980, + 0xf83f21f4, +/* 0x05ed: memx_func_wait_vblank */ + 0x00169800, + 0xf40066b0, + 0x66b0130b, + 0x060bf401, +/* 0x05ff: memx_func_wait_vblank_head1 */ + 0xf12e0ef4, + 0xf4002077, +/* 0x0606: memx_func_wait_vblank_head0 */ + 0x77f1070e, +/* 0x060a: memx_func_wait_vblank_0 */ + 0x67f10008, + 0x64b607c4, + 0x0066cf06, + 0xf40467fd, +/* 0x061a: memx_func_wait_vblank_1 */ + 0x67f1f31b, + 0x64b607c4, + 0x0066cf06, + 0xf40467fd, +/* 0x062a: memx_func_wait_vblank_fini */ + 0x10b6f30b, +/* 0x062f: memx_func_wr32 */ + 0x9800f804, + 0x15980016, + 0x0810b601, + 0x50f960f9, + 0xe0fcd0fc, + 0xb63f21f4, + 0x1bf40242, +/* 0x064b: memx_func_wait */ + 0xf000f8e9, + 0x84b62c87, + 0x0088cf06, + 0x98001e98, + 0x1c98011d, + 0x031b9802, + 0xf41010b6, + 0x00f8a421, +/* 0x0668: memx_func_delay */ + 0xb6001e98, + 0x21f40410, +/* 0x0673: memx_func_train */ + 0xf100f87f, + 0xf1000357, + 0xf1000077, + 0xf0000097, + 0x9eb97093, + 0x0421f402, + 0xf102d8b9, + 0xf42710e7, +/* 0x0692: memx_func_train_loop_outer */ + 0x58e07f21, + 0x83f10101, + 0x97f10200, + 0x93f011e0, + 0xf990f911, 0xfcd0fc80, 0x3f21f4e0, - 0x0560e7f1, - 0xf110e3f0, - 0xf10000d7, - 0xb98000d3, - 0xb7f102dc, - 0xb3f02710, - 0xa421f400, - 0xf402eeb9, - 0xddb90421, - 0x949dff02, + 0x67f150f9, +/* 0x06b2: memx_func_train_loop_inner */ + 0x87f10000, + 0x68ff1111, + 0x10989490, + 0xf10589fd, + 0xf0072097, + 0x90f91093, + 0xd0fc80f9, + 0x21f4e0fc, + 0x8097f13f, + 0x1093f000, + 0xf4029eb9, + 0xd8b90421, + 0x2088c502, + 0x80f990f9, + 0xe0fcd0fc, + 0xf13f21f4, + 0xf0053c97, + 0x87f11093, + 0x83f13002, + 0x90f98000, + 0xd0fc80f9, + 0x21f4e0fc, + 0x60e7f13f, + 0x10e3f005, + 0x0000d7f1, + 0x8000d3f1, + 0xf100dc90, + 0xf08480b7, + 0x21f41eb3, + 0x0057f1a4, + 0xff97f100, + 0x0093f1ff, +/* 0x0731: memx_func_train_loop_4x */ + 0x80a7f183, + 0x10a3f000, + 0xf402aeb9, + 0xd8b90421, + 0xdfb7f102, + 0xffb3f1ff, + 0x048bfdff, + 0x80f9a0f9, + 0xe0fcd0fc, + 0xf13f21f4, + 0xf0053ca7, + 0x87f110a3, + 0x83f13002, + 0xa0f98000, + 0xd0fc80f9, + 0x21f4e0fc, + 0x60e7f13f, + 0x10e3f005, + 0x0000d7f1, + 0x8000d3f1, + 0xf102dcb9, + 0xf02710b7, + 0x21f400b3, + 0x02eeb9a4, + 0xb90421f4, + 0x9dff02dd, + 0x0150b694, + 0xf4045670, + 0x7aa0921e, + 0xa9800bcc, + 0x0160b600, + 0x700470b6, + 0x1ef51066, + 0x50fcff00, 0x700150b6, - 0x1ef40456, - 0xcc7aa092, - 0x00a9800b, - 0xb60160b6, - 0x66700470, - 0x001ef510, - 0xb650fcff, - 0x56700150, - 0xd41ef507, -/* 0x07cf: memx_exec */ - 0xf900f8fe, - 0xb9d0f9e0, - 0xb2b902c1, -/* 0x07d9: memx_exec_next */ - 0x00139802, - 0xe70410b6, - 0xe701f034, - 0xb601e033, - 0x30f00132, - 0xde35980c, - 0x12b855f9, - 0xe41ef406, - 0x98f10b98, - 0xcbbbf20c, - 0xc4b7f102, - 0x06b4b607, - 0xfc00bbcf, - 0xf5e0fcd0, - 0xf8034221, -/* 0x0815: memx_info */ - 0x01c67000, -/* 0x081b: memx_info_data */ - 0xf10e0bf4, - 0xf103ccc7, - 0xf40800b7, -/* 0x0826: memx_info_train */ - 0xc7f10b0e, - 0xb7f10bcc, -/* 0x082e: memx_info_send */ - 0x21f50100, - 0x00f80342, -/* 0x0834: memx_recv */ - 0xf401d6b0, - 0xd6b0980b, - 0xd80bf400, -/* 0x0842: memx_init */ - 0x00f800f8, -/* 0x0844: perf_recv */ -/* 0x0846: perf_init */ - 0x00f800f8, -/* 0x0848: i2c_drive_scl */ - 0xf40036b0, - 0x07f1110b, - 0x04b607e0, - 0x0001d006, - 0x00f804bd, -/* 0x085c: i2c_drive_scl_lo */ - 0x07e407f1, - 0xd00604b6, - 0x04bd0001, -/* 0x086a: i2c_drive_sda */ - 0x36b000f8, - 0x110bf400, - 0x07e007f1, - 0xd00604b6, - 0x04bd0002, -/* 0x087e: i2c_drive_sda_lo */ - 0x07f100f8, - 0x04b607e4, - 0x0002d006, - 0x00f804bd, -/* 0x088c: i2c_sense_scl */ - 0xf10132f4, - 0xb607c437, - 0x33cf0634, - 0x0431fd00, - 0xf4060bf4, -/* 0x08a2: i2c_sense_scl_done */ - 0x00f80131, -/* 0x08a4: i2c_sense_sda */ - 0xf10132f4, - 0xb607c437, - 0x33cf0634, - 0x0432fd00, - 0xf4060bf4, -/* 0x08ba: i2c_sense_sda_done */ - 0x00f80131, -/* 0x08bc: i2c_raise_scl */ - 0x47f140f9, - 0x37f00898, - 0x4821f501, -/* 0x08c9: i2c_raise_scl_wait */ + 0x1ef50756, + 0x00f8fed4, +/* 0x07c4: memx_exec */ + 0xd0f9e0f9, + 0xb902c1b9, +/* 0x07ce: memx_exec_next */ + 0x139802b2, + 0x0410b600, + 0x01f034e7, + 0x01e033e7, + 0xf00132b6, + 0x35980c30, + 0xb855f9de, + 0x1ef40612, + 0xf10b98e4, + 0xbbf20c98, + 0xb7f102cb, + 0xb4b607c4, + 0x00bbcf06, + 0xe0fcd0fc, + 0x033721f5, +/* 0x080a: memx_info */ + 0xc67000f8, + 0x0e0bf401, +/* 0x0810: memx_info_data */ + 0x03ccc7f1, + 0x0800b7f1, +/* 0x081b: memx_info_train */ + 0xf10b0ef4, + 0xf10bccc7, +/* 0x0823: memx_info_send */ + 0xf50100b7, + 0xf8033721, +/* 0x0829: memx_recv */ + 0x01d6b000, + 0xb0980bf4, + 0x0bf400d6, +/* 0x0837: memx_init */ + 0xf800f8d8, +/* 0x0839: perf_recv */ +/* 0x083b: perf_init */ + 0xf800f800, +/* 0x083d: i2c_drive_scl */ + 0x0036b000, + 0xf1110bf4, + 0xb607e007, + 0x01d00604, + 0xf804bd00, +/* 0x0851: i2c_drive_scl_lo */ + 0xe407f100, + 0x0604b607, + 0xbd0001d0, +/* 0x085f: i2c_drive_sda */ + 0xb000f804, + 0x0bf40036, + 0xe007f111, + 0x0604b607, + 0xbd0002d0, +/* 0x0873: i2c_drive_sda_lo */ + 0xf100f804, + 0xb607e407, + 0x02d00604, + 0xf804bd00, +/* 0x0881: i2c_sense_scl */ + 0x0132f400, + 0x07c437f1, + 0xcf0634b6, + 0x31fd0033, + 0x060bf404, +/* 0x0897: i2c_sense_scl_done */ + 0xf80131f4, +/* 0x0899: i2c_sense_sda */ + 0x0132f400, + 0x07c437f1, + 0xcf0634b6, + 0x32fd0033, + 0x060bf404, +/* 0x08af: i2c_sense_sda_done */ + 0xf80131f4, +/* 0x08b1: i2c_raise_scl */ + 0xf140f900, + 0xf0089847, + 0x21f50137, +/* 0x08be: i2c_raise_scl_wait */ + 0xe7f1083d, + 0x21f403e8, + 0x8121f57f, + 0x0901f408, + 0xf40142b6, +/* 0x08d2: i2c_raise_scl_done */ + 0x40fcef1b, +/* 0x08d6: i2c_start */ + 0x21f500f8, + 0x11f40881, + 0x9921f50d, + 0x0611f408, +/* 0x08e7: i2c_start_rep */ + 0xf0300ef4, + 0x21f50037, + 0x37f0083d, + 0x5f21f501, + 0x0076bb08, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x21f550fc, + 0x64b608b1, + 0x1f11f404, +/* 0x0914: i2c_start_send */ + 0xf50037f0, + 0xf1085f21, + 0xf41388e7, + 0x37f07f21, + 0x3d21f500, + 0x88e7f108, + 0x7f21f413, +/* 0x0930: i2c_start_out */ +/* 0x0932: i2c_stop */ + 0x37f000f8, + 0x3d21f500, + 0x0037f008, + 0x085f21f5, + 0x03e8e7f1, + 0xf07f21f4, + 0x21f50137, + 0xe7f1083d, + 0x21f41388, + 0x0137f07f, + 0x085f21f5, + 0x1388e7f1, + 0xf87f21f4, +/* 0x0965: i2c_bitw */ + 0x5f21f500, 0xe8e7f108, 0x7f21f403, - 0x088c21f5, - 0xb60901f4, - 0x1bf40142, -/* 0x08dd: i2c_raise_scl_done */ - 0xf840fcef, -/* 0x08e1: i2c_start */ - 0x8c21f500, - 0x0d11f408, - 0x08a421f5, - 0xf40611f4, -/* 0x08f2: i2c_start_rep */ - 0x37f0300e, - 0x4821f500, - 0x0137f008, - 0x086a21f5, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0xbc21f550, + 0xb121f550, 0x0464b608, -/* 0x091f: i2c_start_send */ - 0xf01f11f4, - 0x21f50037, - 0xe7f1086a, - 0x21f41388, - 0x0037f07f, - 0x084821f5, - 0x1388e7f1, -/* 0x093b: i2c_start_out */ - 0xf87f21f4, -/* 0x093d: i2c_stop */ - 0x0037f000, - 0x084821f5, - 0xf50037f0, - 0xf1086a21, - 0xf403e8e7, + 0xf11811f4, + 0xf41388e7, 0x37f07f21, - 0x4821f501, + 0x3d21f500, 0x88e7f108, 0x7f21f413, - 0xf50137f0, - 0xf1086a21, - 0xf41388e7, - 0x00f87f21, -/* 0x0970: i2c_bitw */ - 0x086a21f5, - 0x03e8e7f1, - 0xbb7f21f4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x08bc21f5, - 0xf40464b6, - 0xe7f11811, +/* 0x09a4: i2c_bitw_out */ +/* 0x09a6: i2c_bitr */ + 0x37f000f8, + 0x5f21f501, + 0xe8e7f108, + 0x7f21f403, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xb121f550, + 0x0464b608, + 0xf51b11f4, + 0xf0089921, + 0x21f50037, + 0xe7f1083d, 0x21f41388, - 0x0037f07f, - 0x084821f5, - 0x1388e7f1, -/* 0x09af: i2c_bitw_out */ - 0xf87f21f4, -/* 0x09b1: i2c_bitr */ - 0x0137f000, - 0x086a21f5, - 0x03e8e7f1, - 0xbb7f21f4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x08bc21f5, - 0xf40464b6, - 0x21f51b11, - 0x37f008a4, - 0x4821f500, - 0x88e7f108, - 0x7f21f413, - 0xf4013cf0, -/* 0x09f6: i2c_bitr_done */ - 0x00f80131, -/* 0x09f8: i2c_get_byte */ - 0xf00057f0, -/* 0x09fe: i2c_get_byte_next */ - 0x54b60847, + 0x013cf07f, +/* 0x09eb: i2c_bitr_done */ + 0xf80131f4, +/* 0x09ed: i2c_get_byte */ + 0x0057f000, +/* 0x09f3: i2c_get_byte_next */ + 0xb60847f0, + 0x76bb0154, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb609a621, + 0x11f40464, + 0x0553fd2b, + 0xf40142b6, + 0x37f0d81b, 0x0076bb01, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b609b1, - 0x2b11f404, - 0xb60553fd, - 0x1bf40142, - 0x0137f0d8, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0x7021f550, - 0x0464b609, -/* 0x0a48: i2c_get_byte_done */ -/* 0x0a4a: i2c_put_byte */ - 0x47f000f8, -/* 0x0a4d: i2c_put_byte_next */ - 0x0142b608, - 0xbb3854ff, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x097021f5, - 0xf40464b6, - 0x46b03411, - 0xd81bf400, + 0x64b60965, +/* 0x0a3d: i2c_get_byte_done */ +/* 0x0a3f: i2c_put_byte */ + 0xf000f804, +/* 0x0a42: i2c_put_byte_next */ + 0x42b60847, + 0x3854ff01, 0xb60076bb, 0x50f90465, 0xbb046594, 0x50bd0256, 0xfc0475fd, - 0xb121f550, + 0x6521f550, 0x0464b609, - 0xbb0f11f4, - 0x36b00076, - 0x061bf401, -/* 0x0aa3: i2c_put_byte_done */ - 0xf80132f4, -/* 0x0aa5: i2c_addr */ - 0x0076bb00, + 0xb03411f4, + 0x1bf40046, + 0x0076bbd8, 0xf90465b6, 0x04659450, 0xbd0256bb, 0x0475fd50, 0x21f550fc, - 0x64b608e1, - 0x2911f404, - 0x012ec3e7, - 0xfd0134b6, - 0x76bb0553, + 0x64b609a6, + 0x0f11f404, + 0xb00076bb, + 0x1bf40136, + 0x0132f406, +/* 0x0a98: i2c_put_byte_done */ +/* 0x0a9a: i2c_addr */ + 0x76bb00f8, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb60a4a21, -/* 0x0aea: i2c_addr_done */ - 0x00f80464, -/* 0x0aec: i2c_acquire_addr */ - 0xb6f8cec7, - 0xe0b702e4, - 0xee980d1c, -/* 0x0afb: i2c_acquire */ - 0xf500f800, - 0xf40aec21, - 0xd9f00421, - 0x3f21f403, -/* 0x0b0a: i2c_release */ - 0x21f500f8, - 0x21f40aec, - 0x03daf004, - 0xf83f21f4, -/* 0x0b19: i2c_recv */ - 0x0132f400, - 0xb6f8c1c7, - 0x16b00214, - 0x3a1ff528, - 0xf413a001, - 0x0032980c, - 0x0ccc13a0, - 0xf4003198, - 0xd0f90231, - 0xd0f9e0f9, - 0x000067f1, - 0x100063f1, - 0xbb016792, + 0xb608d621, + 0x11f40464, + 0x2ec3e729, + 0x0134b601, + 0xbb0553fd, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x0afb21f5, - 0xfc0464b6, - 0x00d6b0d0, - 0x00b31bf5, - 0xbb0057f0, + 0x0a3f21f5, +/* 0x0adf: i2c_addr_done */ + 0xf80464b6, +/* 0x0ae1: i2c_acquire_addr */ + 0xf8cec700, + 0xb702e4b6, + 0x980d1ce0, + 0x00f800ee, +/* 0x0af0: i2c_acquire */ + 0x0ae121f5, + 0xf00421f4, + 0x21f403d9, +/* 0x0aff: i2c_release */ + 0xf500f83f, + 0xf40ae121, + 0xdaf00421, + 0x3f21f403, +/* 0x0b0e: i2c_recv */ + 0x32f400f8, + 0xf8c1c701, + 0xb00214b6, + 0x1ff52816, + 0x13a0013a, + 0x32980cf4, + 0xcc13a000, + 0x0031980c, + 0xf90231f4, + 0xf9e0f9d0, + 0x0067f1d0, + 0x0063f100, + 0x01679210, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xf021f550, + 0x0464b60a, + 0xd6b0d0fc, + 0xb31bf500, + 0x0057f000, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0x9a21f550, + 0x0464b60a, + 0x00d011f5, + 0xbbe0c5c7, 0x65b60076, 0x9450f904, 0x56bb0465, 0xfd50bd02, 0x50fc0475, - 0x0aa521f5, + 0x0a3f21f5, 0xf50464b6, - 0xc700d011, - 0x76bbe0c5, + 0xf000ad11, + 0x76bb0157, 0x0465b600, 0x659450f9, 0x0256bb04, 0x75fd50bd, 0xf550fc04, - 0xb60a4a21, + 0xb60a9a21, 0x11f50464, - 0x57f000ad, - 0x0076bb01, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b60aa5, - 0x8a11f504, - 0x0076bb00, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b609f8, - 0x6a11f404, - 0xbbe05bcb, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x093d21f5, - 0xb90464b6, - 0x74bd025b, -/* 0x0c1f: i2c_recv_not_rd08 */ - 0xb0430ef4, - 0x1bf401d6, - 0x0057f03d, - 0x0aa521f5, - 0xc73311f4, - 0x21f5e0c5, - 0x11f40a4a, - 0x0057f029, - 0x0aa521f5, - 0xc71f11f4, - 0x21f5e0b5, - 0x11f40a4a, - 0x3d21f515, - 0xc774bd09, - 0x1bf408c5, - 0x0232f409, -/* 0x0c5f: i2c_recv_not_wr08 */ -/* 0x0c5f: i2c_recv_done */ - 0xc7030ef4, - 0x21f5f8ce, - 0xe0fc0b0a, - 0x12f4d0fc, - 0x027cb90a, - 0x034221f5, -/* 0x0c74: i2c_recv_exit */ -/* 0x0c76: i2c_init */ + 0x76bb008a, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb609ed21, + 0x11f40464, + 0xe05bcb6a, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0x3221f550, + 0x0464b609, + 0xbd025bb9, + 0x430ef474, +/* 0x0c14: i2c_recv_not_rd08 */ + 0xf401d6b0, + 0x57f03d1b, + 0x9a21f500, + 0x3311f40a, + 0xf5e0c5c7, + 0xf40a3f21, + 0x57f02911, + 0x9a21f500, + 0x1f11f40a, + 0xf5e0b5c7, + 0xf40a3f21, + 0x21f51511, + 0x74bd0932, + 0xf408c5c7, + 0x32f4091b, + 0x030ef402, +/* 0x0c54: i2c_recv_not_wr08 */ +/* 0x0c54: i2c_recv_done */ + 0xf5f8cec7, + 0xfc0aff21, + 0xf4d0fce0, + 0x7cb90a12, + 0x3721f502, +/* 0x0c69: i2c_recv_exit */ +/* 0x0c6b: i2c_init */ + 0xf800f803, +/* 0x0c6d: test_recv */ + 0xd817f100, + 0x0614b605, + 0xb60011cf, + 0x07f10110, + 0x04b605d8, + 0x0001d006, + 0xe7f104bd, + 0xe3f1d900, + 0x21f5134f, + 0x00f80257, +/* 0x0c94: test_init */ + 0x0800e7f1, + 0x025721f5, +/* 0x0c9e: idle_recv */ 0x00f800f8, -/* 0x0c78: test_recv */ - 0x05d817f1, - 0xcf0614b6, - 0x10b60011, - 0xd807f101, - 0x0604b605, - 0xbd0001d0, - 0x00e7f104, - 0x4fe3f1d9, - 0x6221f513, -/* 0x0c9f: test_init */ - 0xf100f802, - 0xf50800e7, - 0xf8026221, -/* 0x0ca9: idle_recv */ -/* 0x0cab: idle */ - 0xf400f800, - 0x17f10031, - 0x14b605d4, - 0x0011cf06, - 0xf10110b6, - 0xb605d407, - 0x01d00604, -/* 0x0cc7: idle_loop */ - 0xf004bd00, - 0x32f45817, -/* 0x0ccd: idle_proc */ -/* 0x0ccd: idle_proc_exec */ - 0xb910f902, - 0x21f5021e, - 0x10fc034b, - 0xf40911f4, - 0x0ef40231, -/* 0x0ce1: idle_proc_next */ - 0x5810b6ef, - 0xf4061fb8, - 0x02f4e61b, - 0x0028f4dd, - 0x00bb0ef4, +/* 0x0ca0: idle */ + 0xf10031f4, + 0xb605d417, + 0x11cf0614, + 0x0110b600, + 0x05d407f1, + 0xd00604b6, + 0x04bd0001, +/* 0x0cbc: idle_loop */ + 0xf45817f0, +/* 0x0cc2: idle_proc */ +/* 0x0cc2: idle_proc_exec */ + 0x10f90232, + 0xf5021eb9, + 0xfc034021, + 0x0911f410, + 0xf40231f4, +/* 0x0cd6: idle_proc_next */ + 0x10b6ef0e, + 0x061fb858, + 0xf4e61bf4, + 0x28f4dd02, + 0xbb0ef400, + 0x00000000, + 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/kernel.fuc index 5cf5be63cbef..ad35fa57be94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/kernel.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/kernel.fuc @@ -225,17 +225,11 @@ intr: nv_iowr(NV_PPWR_SUBINTR, $r9) intr_skip_subintr: - and $r9 $r8 NV_PPWR_INTR_PAUSE - bra z #intr_skip_pause - and $r10 0xffbf - - intr_skip_pause: - and $r9 $r8 NV_PPWR_INTR_USER0 - bra z #intr_skip_user0 - and $r10 0xffbf - - intr_skip_user0: + mov $r9 (NV_PPWR_INTR_USER0 | NV_PPWR_INTR_USER1 | NV_PPWR_INTR_PAUSE) + not b32 $r9 + and $r8 $r9 nv_iowr(NV_PPWR_INTR_ACK, $r8) + pop $r8 mov $flags $r8 pop $r15 diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c index 6326fdc5a48d..2c92ffb5f9d0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c @@ -107,7 +107,7 @@ nv40_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable) { struct nvkm_subdev *subdev = &therm->subdev; struct nvkm_device *device = subdev->device; - u32 mask = enable ? 0x80000000 : 0x0000000; + u32 mask = enable ? 0x80000000 : 0x00000000; if (line == 2) nvkm_mask(device, 0x0010f0, 0x80000000, mask); else if (line == 9) nvkm_mask(device, 0x0015f4, 0x80000000, mask); else { |