diff options
| author | Yue Hin Lau <Yuehin.Lau@amd.com> | 2017-12-07 14:43:24 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-20 14:48:02 -0500 |
| commit | 4b4f8f74a8e36e6be8b13c1573c7d299c3b8cf49 (patch) | |
| tree | 0b11873c8f0747f648eaf6d50b8cd83cac75bd80 /drivers/gpu | |
| parent | 9c6569dea07cd730d424b84c8348d19bb4bb2ff0 (diff) | |
| download | linux-4b4f8f74a8e36e6be8b13c1573c7d299c3b8cf49.tar.bz2 | |
drm/amd/display: integrating optc pseudocode
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h | 19 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 19 |
2 files changed, 37 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index a9ce97fd7f09..eec860fa21e6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -132,6 +132,10 @@ struct dcn_optc_registers { uint32_t OPPBUF_CONTROL; uint32_t OPPBUF_3D_PARAMETERS_0; uint32_t CONTROL; + uint32_t OTG_GSL_WINDOW_X; + uint32_t OTG_GSL_WINDOW_Y; + uint32_t OTG_VUPDATE_KEEPOUT; + uint32_t OTG_DSC_START_POSITION; }; #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ @@ -346,7 +350,20 @@ struct dcn_optc_registers { type OTG_GSL2_EN;\ type OTG_GSL_MASTER_EN;\ type OTG_GSL_FORCE_DELAY;\ - type OTG_GSL_CHECK_ALL_FIELDS; + type OTG_GSL_CHECK_ALL_FIELDS;\ + type OTG_GSL_WINDOW_START_X;\ + type OTG_GSL_WINDOW_END_X;\ + type OTG_GSL_WINDOW_START_Y;\ + type OTG_GSL_WINDOW_END_Y;\ + type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\ + type OTG_GSL_MASTER_MODE;\ + type OTG_MASTER_UPDATE_LOCK_GSL_EN;\ + type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\ + type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\ + type OTG_DSC_START_POSITION_X;\ + type OTG_DSC_START_POSITION_LINE_NUM;\ + type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN; + struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 11a1d3672584..ec312f1a3e55 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -42,6 +42,19 @@ struct dcp_gsl_params { int gsl_master; }; +struct gsl_params { + int gsl0_en; + int gsl1_en; + int gsl2_en; + int gsl_master_en; + int gsl_master_mode; + int master_update_lock_gsl_en; + int gsl_window_start_x; + int gsl_window_end_x; + int gsl_window_start_y; + int gsl_window_end_y; +}; + /* define the structure of Dynamic Refresh Mode */ struct drr_params { uint32_t vertical_total_min; @@ -65,6 +78,12 @@ struct _dlg_otg_param { enum signal_type signal; }; +struct vupdate_keepout_params { + int start_offset; + int end_offset; + int enable; +}; + struct crtc_stereo_flags { uint8_t PROGRAM_STEREO : 1; uint8_t PROGRAM_POLARITY : 1; |