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| author | José Roberto de Souza <jose.souza@intel.com> | 2021-06-30 14:05:22 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2021-07-06 15:10:58 -0400 |
| commit | 995e9bcb42f99b68a45400f51bbbf41bb871ba2f (patch) | |
| tree | 5611e3007d476cf1e8f14a1bfa75b63d20beb1c7 /drivers/gpu/trace | |
| parent | 07b72960d2b4a087ff2445e286159e69742069cc (diff) | |
| download | linux-995e9bcb42f99b68a45400f51bbbf41bb871ba2f.tar.bz2 | |
drm/i915/display/dg1: Correctly map DPLLs during state readout
_DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
bit for phy C and D.
Reusing _cnl_ddi_get_pll() don't take that into cosideration returing
DPLL 0 and 1 for phy C and D.
That is a regression introduced in the refactor done in
commit 351221ffc5e5 ("drm/i915: Move DDI clock readout to
encoder->get_config()").
While at it also dropping the macros previously used, not reusing it
to improve readability.
BSpec: 50286
Fixes: 351221ffc5e5 ("drm/i915: Move DDI clock readout to encoder->get_config()")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210630210522.162674-1-jose.souza@intel.com
(cherry picked from commit 3352d86dcd3336a117630f0c1cfbc6bb8c93e1cf)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/trace')
0 files changed, 0 insertions, 0 deletions