diff options
author | Tao Zhou <tao.zhou1@amd.com> | 2019-08-01 11:41:39 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-02 10:30:38 -0500 |
commit | 13b7c46c18e26182450d01efd0988e5c9fa8260f (patch) | |
tree | 0690c43d9fad706b412823ccb97b3da3c4b0c410 /drivers/gpu/drm | |
parent | 2b671b6049efafc7ae6de9f67acb964b9c534f3a (diff) | |
download | linux-13b7c46c18e26182450d01efd0988e5c9fa8260f.tar.bz2 |
drm/amdgpu: add error address query for umc ras
umc error address query can get ce/ue error address and clear error
status
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e15fedb0ce73..2a4878646b73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -601,6 +601,11 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev, case AMDGPU_RAS_BLOCK__UMC: if (adev->umc.funcs->query_ras_error_count) adev->umc.funcs->query_ras_error_count(adev, &err_data); + /* umc query_ras_error_address is also responsible for clearing + * error status + */ + if (adev->umc.funcs->query_ras_error_address) + adev->umc.funcs->query_ras_error_address(adev, &err_data); break; case AMDGPU_RAS_BLOCK__GFX: if (adev->gfx.funcs->query_ras_error_count) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 24387026fdee..c7647c6988df 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -249,6 +249,11 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); if (adev->umc.funcs->query_ras_error_count) adev->umc.funcs->query_ras_error_count(adev, err_data); + /* umc query_ras_error_address is also responsible for clearing + * error status + */ + if (adev->umc.funcs->query_ras_error_address) + adev->umc.funcs->query_ras_error_address(adev, err_data); amdgpu_ras_reset_gpu(adev, 0); return AMDGPU_RAS_UE; } |