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authorGeorge Shen <george.shen@amd.com>2021-04-16 17:35:07 -0400
committerAlex Deucher <alexander.deucher@amd.com>2021-05-10 18:06:44 -0400
commit05e62b6b6433e1159018eb5862e906a3db24dfcd (patch)
treec35d2f0b07d1c4523c9b458113281d00785f7379 /drivers/gpu/drm
parent70c14a1d7ee4d25d2024967979c8ba618849af54 (diff)
downloadlinux-05e62b6b6433e1159018eb5862e906a3db24dfcd.tar.bz2
drm/amd/display: Filter out YCbCr420 timing if VSC SDP not supported
[Why] Per DP specification, YCbCr420 shall use VSC SDP. [How] For YCbCr420 timings, fail DP mode timing validation if DPCD caps do not indicate VSC SDP colorimetry support. Signed-off-by: George Shen <george.shen@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index ffb4f9027d5e..ced552ed7b8a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2411,6 +2411,12 @@ bool dp_validate_mode_timing(
const struct dc_link_settings *link_setting;
+ /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
+ !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
+ dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
+ return false;
+
/*always DP fail safe mode*/
if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
timing->h_addressable == (uint32_t) 640 &&