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| author | Maxime Ripard <maxime@cerno.tech> | 2020-09-03 10:00:56 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2020-09-07 18:03:44 +0200 |
| commit | f8b13d9bcc674efa3af2d75414fa612936a5a2ea (patch) | |
| tree | 381a9790834c8379f1eaa6914998ed9a7bf50617 /drivers/gpu/drm/vc4/vc4_hvs.c | |
| parent | d2f06525f67d1c224589087feca70c9a214237b2 (diff) | |
| download | linux-f8b13d9bcc674efa3af2d75414fa612936a5a2ea.tar.bz2 | |
drm/vc4: hvs: Make sure our channel is reset
In order to clear our intermediate FIFOs that might end up with a stale
pixel, let's make sure our FIFO channel is reset every time our channel is
setup.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b34c562b36177c758dd2e9d84bceb07689bfbe05.1599120059.git-series.maxime@cerno.tech
Diffstat (limited to 'drivers/gpu/drm/vc4/vc4_hvs.c')
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_hvs.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index efaae60bb323..0f56a7b57916 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -205,6 +205,10 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc, u32 dispbkgndx; u32 dispctrl; + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); + HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); + /* Turn on the scaler, which will wait for vstart to start * compositing. * When feeding the transposer, we should operate in oneshot |