diff options
| author | Thierry Reding <treding@nvidia.com> | 2015-06-10 16:35:44 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 11:18:52 +0100 |
| commit | 553769ff8d8c452cc81a5fe5b0a68cc456c31db3 (patch) | |
| tree | 947cf7fb03aee4b008d81d633dda0c91eb63c1e5 /drivers/gpu/drm/tegra | |
| parent | ad7f2dda38911698deb2cc9ea45362f9a127e3f4 (diff) | |
| download | linux-553769ff8d8c452cc81a5fe5b0a68cc456c31db3.tar.bz2 | |
drm/tegra: dp: Set channel coding on link configuration
Make use of ANSI 8B/10B channel coding if the DisplayPort sink supports
it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
| -rw-r--r-- | drivers/gpu/drm/tegra/dp.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 757a0256592f..ca287b50fad8 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -203,7 +203,7 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link) */ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) { - u8 values[2]; + u8 values[2], value; int err; values[0] = drm_dp_link_rate_to_bw_code(link->rate); @@ -216,5 +216,14 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) if (err < 0) return err; + if (link->caps.channel_coding) + value = DP_SET_ANSI_8B10B; + else + value = 0; + + err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, value); + if (err < 0) + return err; + return 0; } |