diff options
| author | Thierry Reding <treding@nvidia.com> | 2018-02-01 17:47:07 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 11:18:54 +0100 |
| commit | c9533131feebc153feef497ad189d22c00462f4c (patch) | |
| tree | 2f3aefe18c55903b1a15ad7a4b9e5f5e98c5eaff /drivers/gpu/drm/tegra/sor.c | |
| parent | 38b445bc135e7eb3aa7b05316020a1d5194554f9 (diff) | |
| download | linux-c9533131feebc153feef497ad189d22c00462f4c.tar.bz2 | |
drm/tegra: sor: Filter eDP rates
The SOR found on Tegra SoCs does not support all the rates potentially
advertised by eDP 1.4. Make sure that the rates that are not supported
are filtered out.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/sor.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 2023244ad328..9e6a1ab7ef65 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -605,6 +605,30 @@ static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, return clk; } +static void tegra_sor_filter_rates(struct tegra_sor *sor) +{ + struct drm_dp_link *link = &sor->link; + unsigned int i; + + /* Tegra only supports RBR, HBR and HBR2 */ + for (i = 0; i < link->num_rates; i++) { + switch (link->rates[i]) { + case 1620000: + case 2700000: + case 5400000: + break; + + default: + DRM_DEBUG_KMS("link rate %lu kHz not supported\n", + link->rates[i]); + link->rates[i] = 0; + break; + } + } + + drm_dp_link_update_rates(link); +} + static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) { unsigned long timeout; @@ -1897,6 +1921,8 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) if (err < 0) dev_err(sor->dev, "failed to probe eDP link: %d\n", err); + tegra_sor_filter_rates(sor); + err = drm_dp_link_choose(&sor->link, mode, info); if (err < 0) dev_err(sor->dev, "failed to choose link: %d\n", err); |