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| author | zhengbin <zhengbin13@huawei.com> | 2019-11-15 20:12:55 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-11-19 10:12:54 -0500 |
| commit | e9f782dd22c0e17874b8b8e12aafcd3a06810dd0 (patch) | |
| tree | f002893b24fe0a752fe5c170587e66787b0844ac /drivers/gpu/drm/radeon | |
| parent | 5111195ad61791bb22d8650ad7431344d9a00036 (diff) | |
| download | linux-e9f782dd22c0e17874b8b8e12aafcd3a06810dd0.tar.bz2 | |
drm/radeon: remove set but not used variable 'size', 'relocs_chunk'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/radeon/r600_cs.c: In function r600_cs_track_validate_cb:
drivers/gpu/drm/radeon/r600_cs.c:353:22: warning: variable size set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/radeon/r600_cs.c: In function r600_cs_track_validate_db:
drivers/gpu/drm/radeon/r600_cs.c:520:27: warning: variable size set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/radeon/r600_cs.c: In function r600_dma_cs_next_reloc:
drivers/gpu/drm/radeon/r600_cs.c:2345:26: warning: variable relocs_chunk set but not used [-Wunused-but-set-variable]
The first 'size' is not used since commit f30df2fad0c9 ("drm/radeon/r600:
fix tiling issues in CS checker.")
The second 'size' is introduced by commit 88f50c80748b ("drm/radeon/kms:
add htile support to the cs checker v3"), but never used, so remove it.
'relocs_chunk' is not used since commit 9305ede6afe2 ("radeon/kms:
fix dma relocation checking")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index d6c28a5d77ab..49e8266461f8 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -350,7 +350,7 @@ static void r600_cs_track_init(struct r600_cs_track *track) static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) { struct r600_cs_track *track = p->track; - u32 slice_tile_max, size, tmp; + u32 slice_tile_max, tmp; u32 height, height_align, pitch, pitch_align, depth_align; u64 base_offset, base_align; struct array_mode_checker array_check; @@ -360,7 +360,6 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) /* When resolve is used, the second colorbuffer has always 1 sample. */ unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples; - size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; format = G_0280A0_FORMAT(track->cb_color_info[i]); if (!r600_fmt_is_valid_color(format)) { dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", @@ -517,7 +516,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) static int r600_cs_track_validate_db(struct radeon_cs_parser *p) { struct r600_cs_track *track = p->track; - u32 nviews, bpe, ntiles, size, slice_tile_max, tmp; + u32 nviews, bpe, ntiles, slice_tile_max, tmp; u32 height_align, pitch_align, depth_align; u32 pitch = 8192; u32 height = 8192; @@ -564,7 +563,6 @@ static int r600_cs_track_validate_db(struct radeon_cs_parser *p) } ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); } else { - size = radeon_bo_size(track->db_bo); /* pitch in pixels */ pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; @@ -2342,7 +2340,6 @@ int r600_cs_parse(struct radeon_cs_parser *p) int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, struct radeon_bo_list **cs_reloc) { - struct radeon_cs_chunk *relocs_chunk; unsigned idx; *cs_reloc = NULL; @@ -2350,7 +2347,6 @@ int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, DRM_ERROR("No relocation chunk !\n"); return -EINVAL; } - relocs_chunk = p->chunk_relocs; idx = p->dma_reloc_idx; if (idx >= p->nrelocs) { DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |