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| author | Rafał Miłecki <zajec5@gmail.com> | 2013-04-14 01:26:19 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-04-22 10:39:12 -0400 |
| commit | d5169fc4ccfecbfdf3b882be0d2cdf8b057b2eae (patch) | |
| tree | bb1aefdfe83d2dc5c4a40fcf9acc34a467c5fe6e /drivers/gpu/drm/radeon/r600_hdmi.c | |
| parent | d7c605a20ee86a4e8f19ca7b33f7c4f7ba0468bc (diff) | |
| download | linux-d5169fc4ccfecbfdf3b882be0d2cdf8b057b2eae.tar.bz2 | |
drm/radeon: add helpers for masking and setting bits in regs
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_hdmi.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_hdmi.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 21ecc0e12dc4..91582a534f77 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -437,17 +437,15 @@ void r600_hdmi_enable(struct drm_encoder *encoder) hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, - ~AVIVO_TMDSA_CNTL_HDMI_EN); + WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); break; case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, - ~AVIVO_LVTMA_CNTL_HDMI_EN); + WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); break; case ENCODER_OBJECT_ID_INTERNAL_DDI: - WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN); + WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: @@ -504,15 +502,13 @@ void r600_hdmi_disable(struct drm_encoder *encoder) if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - WREG32_P(AVIVO_TMDSA_CNTL, 0, - ~AVIVO_TMDSA_CNTL_HDMI_EN); + WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); break; case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - WREG32_P(AVIVO_LVTMA_CNTL, 0, - ~AVIVO_LVTMA_CNTL_HDMI_EN); + WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); break; case ENCODER_OBJECT_ID_INTERNAL_DDI: - WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN); + WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: break; |