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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2019-03-03 22:29:21 +0200
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2019-03-28 06:12:38 +0200
commit871370308675e477abd57a69ce66ca4730a4249c (patch)
tree6fbd2e830e7d43745a1a02cdf515631aa304af5b /drivers/gpu/drm/omapdrm
parentb764f2f66ed48c7f0df2c4b1350c7973109a1d14 (diff)
downloadlinux-871370308675e477abd57a69ce66ca4730a4249c.tar.bz2
drm: rcar-du: lvds: Adjust operating frequency for D3 and E3
The D3 and E3 SoCs have different pixel clock frequency limits for the LVDS encoder than the other SoCs in the Gen3 family. Adjust the mode fixup implementation accordingly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Diffstat (limited to 'drivers/gpu/drm/omapdrm')
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