diff options
| author | Alexandre Courbot <acourbot@nvidia.com> | 2016-12-14 17:02:46 +0900 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2017-02-17 15:14:32 +1000 |
| commit | b2888c650e61d03bbfc8325662cff660b40b39ba (patch) | |
| tree | bbe02c7bd2be9ee33cea1ad6bc703dc904b5115e /drivers/gpu/drm/nouveau/nvkm | |
| parent | 9d896f3e41a6093a843ce668c97159367c1e4573 (diff) | |
| download | linux-b2888c650e61d03bbfc8325662cff660b40b39ba.tar.bz2 | |
drm/nouveau/secboot: safer zeroing of BL descriptors
Perform the zeroing of BL descriptors in the caller function instead of
trusting each generator will do it. This could avoid a few pulled hairs.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c | 2 |
2 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index 741f3fc88565..ef8ff7f67e7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -105,7 +105,6 @@ acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr, addr_code = (base + pdesc->app_resident_code_offset) >> 8; addr_data = (base + pdesc->app_resident_data_offset) >> 8; - memset(desc, 0, sizeof(*desc)); desc->ctx_dma = FALCON_DMAIDX_UCODE; desc->code_dma_base = lower_32_bits(addr_code); desc->non_sec_code_off = pdesc->app_resident_code_offset; @@ -354,6 +353,7 @@ acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, &img->lsb_header, sizeof(img->lsb_header)); /* Generate and write BL descriptor */ + memset(gdesc, 0, ls_func->bl_desc_size); ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc); nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off, @@ -515,7 +515,6 @@ acr_r352_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc, struct acr_r352_flcn_bl_desc *bl_desc = _bl_desc; u64 addr_code, addr_data; - memset(bl_desc, 0, sizeof(*bl_desc)); addr_code = offset >> 8; addr_data = (offset + hdr->data_dma_base) >> 8; @@ -713,6 +712,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_secboot *sb, code_size, hsbl_desc->start_tag, 0, false); /* Generate the BL header */ + memset(bl_desc, 0, bl_desc_size); acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset); /* diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c index 4b9a688965e5..f0aff1d98474 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c @@ -75,7 +75,6 @@ acr_r361_generate_flcn_bl_desc(const struct nvkm_acr *acr, addr_code = base + pdesc->app_resident_code_offset; addr_data = base + pdesc->app_resident_data_offset; - memset(desc, 0, sizeof(*desc)); desc->ctx_dma = FALCON_DMAIDX_UCODE; desc->code_dma_base = u64_to_flcn64(addr_code); desc->non_sec_code_off = pdesc->app_resident_code_offset; @@ -91,7 +90,6 @@ acr_r361_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc, { struct acr_r361_flcn_bl_desc *bl_desc = _bl_desc; - memset(bl_desc, 0, sizeof(*bl_desc)); bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; bl_desc->code_dma_base = u64_to_flcn64(offset); bl_desc->non_sec_code_off = hdr->non_sec_code_off; |