summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c
diff options
context:
space:
mode:
authorBen Skeggs <bskeggs@redhat.com>2022-06-01 20:47:52 +1000
committerBen Skeggs <bskeggs@redhat.com>2022-11-09 10:44:58 +1000
commit2541626cfb794e57ba0575a6920826f591f7ced0 (patch)
treede53edee6959486a2ce6e8085820680cc14a41ba /drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c
parente3f324956a32d08a9361ee1e3beca383f1b01eba (diff)
downloadlinux-2541626cfb794e57ba0575a6920826f591f7ced0.tar.bz2
drm/nouveau/acr: use common falcon HS FW code for ACR FWs
Adds context binding and support for FWs with a bootloader to the code that was added to load VPR scrubber HS binaries, and ports ACR over to using all of it. - gv100 split from gp108 to handle FW exit status differences Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c12
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c
index 47c7412f86e8..cd3148360996 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c
@@ -30,14 +30,10 @@ gp102_pmu_flcn = {
.reset_eng = gp102_flcn_reset_eng,
.reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,
.debug = 0xc08,
- .fbif = 0xe00,
- .load_imem = nvkm_falcon_v1_load_imem,
- .load_dmem = nvkm_falcon_v1_load_dmem,
- .read_dmem = nvkm_falcon_v1_read_dmem,
- .bind_context = nvkm_falcon_v1_bind_context,
- .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
- .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
- .set_start_addr = nvkm_falcon_v1_set_start_addr,
+ .bind_inst = gm200_pmu_flcn_bind_inst,
+ .bind_stat = gm200_flcn_bind_stat,
+ .imem_pio = &gm200_flcn_imem_pio,
+ .dmem_pio = &gm200_flcn_dmem_pio,
.start = nvkm_falcon_v1_start,
.cmdq = { 0x4a0, 0x4b0, 4 },
.msgq = { 0x4c8, 0x4cc, 0 },