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| author | Ben Skeggs <bskeggs@redhat.com> | 2020-01-15 06:34:22 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2020-01-15 10:50:29 +1000 |
| commit | 22dcda45a3d1dfe6eeb4ab0a3b9aaa2333cb649d (patch) | |
| tree | fc4d20a93edce93ca252d9f0663cd620e65d1c51 /drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c | |
| parent | ebe52a58acca308142ba2811e50a1b3bf047240d (diff) | |
| download | linux-22dcda45a3d1dfe6eeb4ab0a3b9aaa2333cb649d.tar.bz2 | |
drm/nouveau/acr: implement new subdev to replace "secure boot"
ACR is responsible for managing the firmware for LS (Low Secure) falcons,
this was previously handled in the driver by SECBOOT.
This rewrite started from some test code that attempted to replicate the
procedure RM uses in order to debug early Turing ACR firmwares that were
provided by NVIDIA for development.
Compared with SECBOOT, the code is structured into more individual steps,
with the aim of making the process easier to follow/debug, whilst making
it possible to support newer firmware versions that may have a different
binary format or API interface.
The HS (High Secure) binary(s) are now booted earlier in device init, to
match the behaviour of RM, whereas SECBOOT would delay this until we try
to boot the first LS falcon.
There's also additional debugging features available, with the intention
of making it easier to solve issues during FW/HW bring-up in the future.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c index e22211906b42..a3db2a95ff9a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c @@ -27,8 +27,14 @@ #include <nvif/class.h> +#include <nvfw/flcn.h> + static const struct nvkm_acr_lsf_func gp10b_gr_gpccs_acr = { + .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD, + .bld_size = sizeof(struct flcn_bl_dmem_desc), + .bld_write = gm20b_gr_acr_bld_write, + .bld_patch = gm20b_gr_acr_bld_patch, }; static const struct gf100_gr_func |