diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2015-08-20 14:54:08 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2015-08-28 12:40:11 +1000 |
| commit | bfee3f3d97db88bfb732735eb4955ad3381ac758 (patch) | |
| tree | 446fe6e7af9404c3419ed2d551d97af3c4491628 /drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | |
| parent | 6189f1b0938dc0621c27494031b83ffae566e318 (diff) | |
| download | linux-bfee3f3d97db88bfb732735eb4955ad3381ac758.tar.bz2 | |
drm/nouveau/gr: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 897628062d58..6b9c84f8f12d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -35,34 +35,34 @@ gm20b_gr_sclass[] = { }; static void -gm20b_gr_init_gpc_mmu(struct gf100_gr_priv *priv) +gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) { u32 val; /* TODO this needs to be removed once secure boot works */ if (1) { - nv_wr32(priv, 0x100ce4, 0xffffffff); + nv_wr32(gr, 0x100ce4, 0xffffffff); } /* TODO update once secure boot works */ - val = nv_rd32(priv, 0x100c80); + val = nv_rd32(gr, 0x100c80); val &= 0xf000087f; - nv_wr32(priv, 0x418880, val); - nv_wr32(priv, 0x418890, 0); - nv_wr32(priv, 0x418894, 0); + nv_wr32(gr, 0x418880, val); + nv_wr32(gr, 0x418890, 0); + nv_wr32(gr, 0x418894, 0); - nv_wr32(priv, 0x4188b0, nv_rd32(priv, 0x100cc4)); - nv_wr32(priv, 0x4188b4, nv_rd32(priv, 0x100cc8)); - nv_wr32(priv, 0x4188b8, nv_rd32(priv, 0x100ccc)); + nv_wr32(gr, 0x4188b0, nv_rd32(gr, 0x100cc4)); + nv_wr32(gr, 0x4188b4, nv_rd32(gr, 0x100cc8)); + nv_wr32(gr, 0x4188b8, nv_rd32(gr, 0x100ccc)); - nv_wr32(priv, 0x4188ac, nv_rd32(priv, 0x100800)); + nv_wr32(gr, 0x4188ac, nv_rd32(gr, 0x100800)); } static void -gm20b_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv) +gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) { - nv_wr32(priv, 0x419e44, 0xdffffe); - nv_wr32(priv, 0x419e4c, 0x5); + nv_wr32(gr, 0x419e44, 0xdffffe); + nv_wr32(gr, 0x419e4c, 0x5); } struct nvkm_oclass * |