diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2022-06-01 20:47:38 +1000 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2022-11-09 10:44:50 +1000 |
commit | 06db7fded6dec88772a65c5a39af12ba4dc2ad38 (patch) | |
tree | d00ff73679dd75931c7625880903e1b301184600 /drivers/gpu/drm/nouveau/include/nvif/if0020.h | |
parent | 7ac293328122075a2afc40a4089e7afc6cbc26eb (diff) | |
download | linux-06db7fded6dec88772a65c5a39af12ba4dc2ad38.tar.bz2 |
drm/nouveau/fifo: add new channel classes
Exposes a bunch of the new features that became possible as a result
of the earlier commits. DRM will build on this in the future to add
support for features such as SCG ("async compute") and multi-device
rendering, as part of the work necessary to be able to write a half-
decent vulkan driver - finally.
For the moment, this just crudely ports DRM to the API changes.
- channel class interfaces now the same for all HW classes
- channel group class exposed (SCG)
- channel runqueue selector exposed (SCG)
- channel sub-device id control exposed (multi-device rendering)
- channel names in logging will reflect creating process, not fd owner
- explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer
- drm is smarter about determining the appropriate channel class to use
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/include/nvif/if0020.h')
-rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/if0020.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0020.h b/drivers/gpu/drm/nouveau/include/nvif/if0020.h index 1893b8aa0abb..085e0ae8a450 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0020.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0020.h @@ -2,6 +2,38 @@ #ifndef __NVIF_IF0020_H__ #define __NVIF_IF0020_H__ +union nvif_chan_args { + struct nvif_chan_v0 { + __u8 version; + __u8 namelen; + __u8 runlist; + __u8 runq; + __u8 priv; + __u8 pad05; + __u16 devm; + __u64 vmm; + + __u64 ctxdma; + __u64 offset; + __u64 length; + + __u64 huserd; + __u64 ouserd; + + __u32 token; + __u16 chid; + __u8 pad3e; +#define NVIF_CHAN_V0_INST_APER_VRAM 0 +#define NVIF_CHAN_V0_INST_APER_HOST 1 +#define NVIF_CHAN_V0_INST_APER_NCOH 2 +#define NVIF_CHAN_V0_INST_APER_INST 0xff + __u8 aper; + __u64 inst; + + __u8 name[]; + } v0; +}; + union nvif_chan_event_args { struct nvif_chan_event_v0 { __u8 version; |