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authorDaniel Vetter <daniel.vetter@ffwll.ch>2021-08-05 12:47:01 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2021-08-30 11:02:14 +0200
commitf1b3f696a084534a87619ac1a6aa81e78bf86437 (patch)
tree33f4cec6a70be400345565470450a7158cc1c217 /drivers/gpu/drm/msm/msm_gem_submit.c
parent80bcfbd3766881930e9a731367da14fd763e9086 (diff)
downloadlinux-f1b3f696a084534a87619ac1a6aa81e78bf86437.tar.bz2
drm/msm: Don't break exclusive fence ordering
There's only one exclusive slot, and we must not break the ordering. Adding a new exclusive fence drops all previous fences from the dma_resv. To avoid violating the signalling order we err on the side of over-synchronizing by waiting for the existing fences, even if userspace asked us to ignore them. A better fix would be to us a dma_fence_chain or _array like e.g. amdgpu now uses, but - msm has a synchronous dma_fence_wait for anything from another context, so doesn't seem to care much, - and it probably makes sense to lift this into dma-resv.c code as a proper concept, so that drivers don't have to hack up their own solution each on their own. v2: Improve commit message per Lucas' suggestion. Cc: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Link: https://patchwork.freedesktop.org/patch/msgid/20210805104705.862416-17-daniel.vetter@ffwll.ch
Diffstat (limited to 'drivers/gpu/drm/msm/msm_gem_submit.c')
-rw-r--r--drivers/gpu/drm/msm/msm_gem_submit.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
index a1d539d8fb58..924b01b9c105 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -330,7 +330,8 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)
return ret;
}
- if (no_implicit)
+ /* exclusive fences must be ordered */
+ if (no_implicit && !write)
continue;
ret = drm_sched_job_add_implicit_dependencies(&submit->base,