diff options
| author | Krishna Manikandan <mkrishn@codeaurora.org> | 2021-05-27 10:37:56 +0530 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-06-23 07:32:16 -0700 |
| commit | a1f2ba60eace242fd034173db3762f342a824a2e (patch) | |
| tree | 0a3112346ab09fc8e3d2dbb7032c7fe41fbe8794 /drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | |
| parent | 5b702d787b47e19f5aebb4f11360678493759a3b (diff) | |
| download | linux-a1f2ba60eace242fd034173db3762f342a824a2e.tar.bz2 | |
drm/msm/disp/dpu1: avoid perf update in frame done event
Crtc perf update from frame event work can result in
wrong bandwidth and clock update from dpu if the work
is scheduled after the swap state has happened.
Avoid such issues by moving perf update to complete
commit once the frame is accepted by the hardware.
Fixes: a29c8c024165 ("drm/msm/disp/dpu1: fix display underruns during modeset")
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/1622092076-5100-1-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 3e54dafc2f8a..9a5c70c87cc8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -406,9 +406,6 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) fevent->event); } - if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE) - dpu_core_perf_crtc_update(crtc, 0, false); - if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE | DPU_ENCODER_FRAME_EVENT_ERROR)) frame_done = true; @@ -476,6 +473,7 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event) void dpu_crtc_complete_commit(struct drm_crtc *crtc) { trace_dpu_crtc_complete_commit(DRMID(crtc)); + dpu_core_perf_crtc_update(crtc, 0, false); _dpu_crtc_complete_flip(crtc); } |