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| author | Vladimir Lypak <vladimir.lypak@gmail.com> | 2021-12-12 16:03:17 +0000 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-12-17 15:09:46 -0800 |
| commit | 6ed95285382d6f90a3c3a11d5806a5eb7db715c3 (patch) | |
| tree | 801c2ec474a82a10eb60f304e71ac90b8fdec304 /drivers/gpu/drm/msm/adreno | |
| parent | 6bf7805321b96e4144c1232d7c3f66b2dce35761 (diff) | |
| download | linux-6ed95285382d6f90a3c3a11d5806a5eb7db715c3.tar.bz2 | |
drm/msm/a5xx: Fix missing CP_PROTECT for SMMU on A540
A CP_PROTECT entry for SMMU registers is missing for A540. According to
downstream sources its length is same as on A530 - 0x20000 bytes.
On all other revisions SMMU region length is 0x10000 bytes. Despite
this, we setup region of length 0x20000 on all revisions. This doesn't
cause any issues on those GPUs. As for preventing accesses to the region
from protected mode it was tested to work the same.
This patch drops the "if" condition in setup of CP_PROTECT entry because
it already includes all supported revisions except A540.
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Link: https://lore.kernel.org/r/20211212160333.980343-2-vladimir.lypak@gmail.com
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index e3f25be4e170..3d28fcf841a6 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -858,10 +858,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* UCHE */ gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); - if (adreno_is_a506(adreno_gou) || adreno_is_a508(adreno_gpu) || - adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) || - adreno_is_a512(adreno_gpu) || adreno_is_a530(adreno_gpu)) - gpu_write(gpu, REG_A5XX_CP_PROTECT(17), + /* SMMU */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(17), ADRENO_PROTECT_RW(0x10000, 0x8000)); gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0); |