diff options
| author | Jordan Crouse <jcrouse@codeaurora.org> | 2016-11-28 12:28:29 -0700 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2016-11-28 15:14:12 -0500 |
| commit | fb039981923950716c4e5bccef19d1716ffd298e (patch) | |
| tree | 1f1d7626daba1bbc4a05ed7018c08f88f0d767f6 /drivers/gpu/drm/msm/adreno/a3xx_gpu.c | |
| parent | ae53a829d5c9715b651ee33e266eaa4454e7f2ad (diff) | |
| download | linux-fb039981923950716c4e5bccef19d1716ffd298e.tar.bz2 | |
drm/msm: Add adreno_gpu_write64()
Add a new generic function to write a "64" bit value. This isn't
actually a 64 bit operation, it just writes the upper and lower
32 bit of a 64 bit value to a specified LO and HI register. If
a particular target doesn't support one of the registers it can
mark that register as SKIP and writes/reads from that register
will be quietly dropped.
This can be immediately put in place for the ringbuffer base and
the RPTR address. Both writes are converted to use
adreno_gpu_write64() with their respective high and low registers
and the high register appropriately marked as SKIP for both 32 bit
targets (a3xx and a4xx). When a5xx comes it will define valid target
registers for the 'hi' option and everything else will just work.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a3xx_gpu.c')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index ff6489444423..b999349b7d2d 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -430,7 +430,9 @@ static void a3xx_dump(struct msm_gpu *gpu) /* Register offset defines for A3XX */ static const unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL), |