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| author | Julien Masson <jmasson@baylibre.com> | 2019-08-22 16:43:41 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2019-08-22 17:54:05 +0200 |
| commit | 528a25d040bc2123fe5a9f8697a60f8bff40af0a (patch) | |
| tree | 506b2ee5efb635bef3ab47a7cd8e2355d43af74a /drivers/gpu/drm/meson/meson_plane.c | |
| parent | ade925995b172f1d7410d1c665b2f47c5e99bef0 (diff) | |
| download | linux-528a25d040bc2123fe5a9f8697a60f8bff40af0a.tar.bz2 | |
drm: meson: use match data to detect vpu compatibility
This patch introduce new enum which contains all VPU family (GXBB,
GXL, GXM and G12A).
This enum is used to detect the VPU compatible with the device.
We only need to set .data to the corresponding enum in the device
table, no need to check .compatible string anymore.
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87imqpz21w.fsf@masson.i-did-not-set--mail-host-address--so-tickle-me
Diffstat (limited to 'drivers/gpu/drm/meson/meson_plane.c')
| -rw-r--r-- | drivers/gpu/drm/meson/meson_plane.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c index b9e1e117fb85..ed543227b00d 100644 --- a/drivers/gpu/drm/meson/meson_plane.c +++ b/drivers/gpu/drm/meson/meson_plane.c @@ -138,7 +138,7 @@ static void meson_plane_atomic_update(struct drm_plane *plane, OSD_ENDIANNESS_LE); /* On GXBB, Use the old non-HDR RGB2YUV converter */ - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; switch (fb->format->format) { @@ -292,7 +292,7 @@ static void meson_plane_atomic_update(struct drm_plane *plane, priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1; priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1; - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1; priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1; priv->viu.osb_blend0_size = dst_h << 16 | dst_w; @@ -308,8 +308,8 @@ static void meson_plane_atomic_update(struct drm_plane *plane, if (!meson_plane->enabled) { /* Reset OSD1 before enabling it on GXL+ SoCs */ - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) meson_viu_osd1_reset(priv); meson_plane->enabled = true; @@ -327,7 +327,7 @@ static void meson_plane_atomic_disable(struct drm_plane *plane, struct meson_drm *priv = meson_plane->priv; /* Disable OSD1 */ - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0, priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); else |