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| author | Jitao Shi <jitao.shi@mediatek.com> | 2019-09-19 14:58:06 +0800 |
|---|---|---|
| committer | CK Hu <ck.hu@mediatek.com> | 2019-10-07 12:29:39 +0800 |
| commit | 75374fc2c152ef42c45c6bf716743d5f5bb6d24d (patch) | |
| tree | a22309bbb843817cd7b94d793f917a16e41e6e7f /drivers/gpu/drm/mediatek/mtk_dsi.c | |
| parent | 2f501cc0b020b9d991128a70e26c84552121a31d (diff) | |
| download | linux-75374fc2c152ef42c45c6bf716743d5f5bb6d24d.tar.bz2 | |
drm/mediatek: add dphy reset after setting lanes number
Add dphy reset after setting lanes number to avoid dphy fifo effor.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Diffstat (limited to 'drivers/gpu/drm/mediatek/mtk_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/mediatek/mtk_dsi.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 989e55f3e0c0..c62b9b496036 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -39,6 +39,7 @@ #define DSI_CON_CTRL 0x10 #define DSI_RESET BIT(0) #define DSI_EN BIT(1) +#define DPHY_RESET BIT(2) #define DSI_MODE_CTRL 0x14 #define MODE (3) @@ -282,6 +283,12 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi) mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0); } +static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi) +{ + mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET); + mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0); +} + static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) { mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); @@ -652,6 +659,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_phy_timconfig(dsi); mtk_dsi_rxtx_control(dsi); + usleep_range(30, 100); + mtk_dsi_reset_dphy(dsi); mtk_dsi_ps_control_vact(dsi); mtk_dsi_set_vm_cmd(dsi); mtk_dsi_config_vdo_timing(dsi); |