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| author | Matt Roper <matthew.d.roper@intel.com> | 2022-10-14 16:02:35 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-10-17 10:16:05 -0700 |
| commit | cf35f6afb92643633f4ecbb386ab8a572cca0386 (patch) | |
| tree | b6247ccc620646af9f7e4972d3994863b41df2cc /drivers/gpu/drm/ingenic | |
| parent | 46c507f03a46108e5a93acc06a060601ac9b83d6 (diff) | |
| download | linux-cf35f6afb92643633f4ecbb386ab8a572cca0386.tar.bz2 | |
drm/i915/guc: Handle save/restore of MCR registers explicitly
MCR registers can be placed on the GuC's save/restore list, but at the
moment they are always handled in a multicast manner (i.e., the GuC
reads one instance to save the value and then does a multicast write to
restore that single value to all instances). In the future the GuC will
probably give us an alternate interface to do unicast per-instance
save/restore operations, so we should be very clear about which
registers on the list are MCR registers (and in the future which
save/restore behavior we want for them).
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-11-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/ingenic')
0 files changed, 0 insertions, 0 deletions