diff options
| author | Vinay Belgaumkar <vinay.belgaumkar@intel.com> | 2022-04-15 15:40:23 -0700 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2022-04-19 11:33:47 -0700 |
| commit | dfa57ecf77c66eb28ac7760f582bfd7d4183c429 (patch) | |
| tree | d4368dd3155172d31eae76ad034b78f68bd42515 /drivers/gpu/drm/i915 | |
| parent | c6b41c4d9becce74bae50b461011250b9ae004a0 (diff) | |
| download | linux-dfa57ecf77c66eb28ac7760f582bfd7d4183c429.tar.bz2 | |
drm/i915/guc: Apply Wa_16011777198
Enable GuC Wa to reset RCS/CCS before it goes into RC6.
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220415224025.3693037-5-umesh.nerlige.ramappa@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index fd04c4cd9d44..830889349756 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -310,6 +310,11 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) if (GRAPHICS_VER(gt->i915) == 12) flags |= GUC_WA_PRE_PARSER; + /* Wa_16011777198:dg2 */ + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || + IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) + flags |= GUC_WA_RCS_RESET_BEFORE_RC6; + return flags; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h index fe5751f67b19..126e67ea1619 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h @@ -100,6 +100,7 @@ #define GUC_CTL_WA 1 #define GUC_WA_GAM_CREDITS BIT(10) #define GUC_WA_DUAL_QUEUE BIT(11) +#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13) #define GUC_WA_PRE_PARSER BIT(14) #define GUC_WA_POLLCS BIT(18) |