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| author | Praveen Paneri <praveen.paneri@intel.com> | 2017-08-03 23:02:10 +0530 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-03 12:30:23 -0700 |
| commit | 32087d1425887e2d51e8c77ff9849d73f6384457 (patch) | |
| tree | 32da80d060922151269d0c6d64c1b3ab4d18972e /drivers/gpu/drm/i915 | |
| parent | 23247d715d3cf679cac24d1c4de2d76774a2a495 (diff) | |
| download | linux-32087d1425887e2d51e8c77ff9849d73f6384457.tar.bz2 | |
drm/i915: enable WaDisableDopClkGating for skl
This WA is required when decoupled frequencies for slice and unslice
are enabled. This disables DOP clock gating for skl.
v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
the hang issue is originally reported) to avoid rare hangs (David)
v3: as per WaDatabase, enable it only for SKL (Rodrigo)
Cc: David Weinehall <david.weinehall@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1501781530-8186-1-git-send-email-praveen.paneri@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8711c1f04079..6e393b217450 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | ILK_DPFC_DISABLE_DUMMY0); + + if (IS_SKYLAKE(dev_priv)) { + /* WaDisableDopClockGating */ + I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) + & ~GEN7_DOP_CLOCK_GATE_ENABLE); + } } static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) |