diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-07 22:21:42 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-08 14:29:39 +0200 |
| commit | 8271b2ef71aaabac452dc03a6cbe8960cbea4247 (patch) | |
| tree | 2cf522d43f154bc33dfcf0ffa2073f8407e4ede1 /drivers/gpu/drm/i915/intel_sprite.c | |
| parent | 5f29ab23046a4bb08a850e41bdb579b2cb59421d (diff) | |
| download | linux-8271b2ef71aaabac452dc03a6cbe8960cbea4247.tar.bz2 | |
drm/i915: Track pipe csc enable in crtc state
Just like we did for pipe gamma, let's also track the pipe csc
state. The hardware only exists on ILK+, and currently we always
enable it on hsw+ and never on any other platforms. Just like
with pipe gamma, the primary plane control register is used
for the readout on pre-SKL, and the pipe bottom color register
on SKL+.
v2: Rebase
v3: Allow fastboot with csc_enable changes (Maarten)
Deal with HAS_GMCH
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-4-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sprite.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_sprite.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index db373e3ac601..610398607e8e 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -921,13 +921,12 @@ vlv_plane_get_hw_state(struct intel_plane *plane, static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); u32 sprctl = 0; if (crtc_state->gamma_enable) sprctl |= SPRITE_GAMMA_ENABLE; - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) + if (crtc_state->csc_enable) sprctl |= SPRITE_PIPE_CSC_ENABLE; return sprctl; @@ -1118,6 +1117,9 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) if (crtc_state->gamma_enable) dvscntr |= DVS_GAMMA_ENABLE; + if (crtc_state->csc_enable) + dvscntr |= DVS_PIPE_CSC_ENABLE; + return dvscntr; } |