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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2018-12-28 17:16:38 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-12-31 15:35:45 +0000 |
| commit | d9cad2206abf4f2986c2f74ae5cc4e2415232091 (patch) | |
| tree | 8f377a54e96c3befe57507c4ecf02cc0e7ed8f03 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | 2f0c733b353c2bf6175a4b3cc7d8fb66e86d69f0 (diff) | |
| download | linux-d9cad2206abf4f2986c2f74ae5cc4e2415232091.tar.bz2 | |
drm/i915/ringbuffer: Remove irq-seqno w/a for gen6 xcs
The MI_FLUSH_DW does appear coherent with the following
MI_USER_INTERRUPT, but only on Sandybridge. Ivybridge requires a heavier
hammer, but on Sandybridge we can stop requiring the irq_seqno barrier.
Testcase: igt/gem_sync
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181228171641.16531-3-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 1b9264883a8d..2fb3a364c390 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2260,7 +2260,8 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb; engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz; - engine->irq_seqno_barrier = gen6_seqno_barrier; + if (!IS_GEN(dev_priv, 6)) + engine->irq_seqno_barrier = gen6_seqno_barrier; } else { engine->emit_flush = bsd_ring_flush; if (IS_GEN(dev_priv, 5)) @@ -2285,7 +2286,8 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb; engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz; - engine->irq_seqno_barrier = gen6_seqno_barrier; + if (!IS_GEN(dev_priv, 6)) + engine->irq_seqno_barrier = gen6_seqno_barrier; return intel_init_ring_buffer(engine); } |