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| author | Vandita Kulkarni <vandita.kulkarni@intel.com> | 2019-06-19 16:31:33 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-06-20 13:17:52 -0700 |
| commit | 6a7bafe8fdb6019101ec90a5f5ddeea6f58d1158 (patch) | |
| tree | b7fd6df4cbbf19abf374b39a64e8a927d6b41960 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 60a0933bff57af52f99a17cbe9f0bc5d27771236 (diff) | |
| download | linux-6a7bafe8fdb6019101ec90a5f5ddeea6f58d1158.tar.bz2 | |
drm/i915/ehl/dsi: Set lane latency optimization for DW1
EHL has 2 additional steps in the DSI sequence, this is one of then
the lane latency optimization for DW1.
BSpec: 20597
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619233134.20009-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 02c7f8c6c20b..969c3b23d519 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1896,6 +1896,8 @@ enum i915_power_well_id { #define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port)) #define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port)) #define COMMON_KEEPER_EN (1 << 26) +#define LATENCY_OPTIM_MASK (0x3 << 2) +#define LATENCY_OPTIM_VAL(x) ((x) << 2) /* CNL/ICL Port TX registers */ #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 |