summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/gt/uc/intel_guc.c
diff options
context:
space:
mode:
authorMatt Roper <matthew.d.roper@intel.com>2022-06-07 17:51:08 -0700
committerMatt Roper <matthew.d.roper@intel.com>2022-06-08 07:25:03 -0700
commitc5cb0002d14b6f7aabaf7d67d0515fe70aea7167 (patch)
tree5eb3703ff328d327c3ec8f5a5a699299e980163f /drivers/gpu/drm/i915/gt/uc/intel_guc.c
parent5821a0bbb4c39960975d29d6b58ae290088db0ed (diff)
downloadlinux-c5cb0002d14b6f7aabaf7d67d0515fe70aea7167.tar.bz2
drm/i915: More PVC+DG2 workarounds
A new PVC+DG2 workaround has appeared recently: - Wa_16015675438 And a couple existing DG2 workarounds have been extended to PVC: - Wa_14015795083 - Wa_18018781329 Note that Wa_16015675438 asks us to program a register that is in the 0x2xxx range typically associated with the RCS engine, even though PVC does not have an RCS. By default the GuC will think we've made a mistake and throw an exception when it sees this register on a CCS engine's save/restore list, so we need to pass an extra GuC control flag to tell it that this is expected and not a problem. Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220608005108.3717895-1-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/uc/intel_guc.c')
-rw-r--r--drivers/gpu/drm/i915/gt/uc/intel_guc.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2c4ad4a65089..35887cb53201 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -327,6 +327,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER))
flags |= GUC_WA_CONTEXT_ISOLATION;
+ /* Wa_16015675438 */
+ if (!RCS_MASK(gt))
+ flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
+
return flags;
}