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| author | Maxime Ripard <maxime@cerno.tech> | 2022-09-14 12:22:18 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2022-09-14 12:22:18 +0100 |
| commit | a108772d03d8bdb43258218b00bfe43bbe1e8800 (patch) | |
| tree | 11b1f413ab384f2b5de0773f01b6886e2c601f8b /drivers/gpu/drm/i915/gt/intel_gt_regs.h | |
| parent | 75cebd664d57a78af3e46c14bd2659df0a08847b (diff) | |
| parent | 213cb76ddc8b875e772f9f4d173feefa122716af (diff) | |
| download | linux-a108772d03d8bdb43258218b00bfe43bbe1e8800.tar.bz2 | |
Merge drm/drm-next into drm-misc-next
We need 6.0-rc1 to merge the backlight rework PR.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gt_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_regs.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 60d6eb5f245b..d414785003cc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -259,6 +259,9 @@ #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) +#define DRAW_WATERMARK _MMIO(0x26c0) +#define VERT_WM_VAL REG_GENMASK(9, 0) + #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ #define RENDER_HWS_PGA_GEN7 _MMIO(0x4080) @@ -374,6 +377,9 @@ #define CHICKEN_RASTER_1 _MMIO(0x6204) #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) +#define CHICKEN_RASTER_2 _MMIO(0x6208) +#define TBIMR_FAST_CLIP REG_BIT(5) + #define VFLSKPD _MMIO(0x62a8) #define DIS_OVER_FETCH_CACHE REG_BIT(1) #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) @@ -1007,6 +1013,8 @@ #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9) #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) +#define GUCPMTIMESTAMP _MMIO(0xc3e8) + #define __GEN9_RCS0_MOCS0 0xc800 #define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4) #define __GEN9_VCS0_MOCS0 0xc900 @@ -1078,6 +1086,7 @@ #define GEN10_SAMPLER_MODE _MMIO(0xe18c) #define ENABLE_SMALLPL REG_BIT(15) +#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) @@ -1101,6 +1110,8 @@ #define GEN12_DISABLE_TDL_PUSH REG_BIT(9) #define GEN11_DIS_PICK_2ND_EU REG_BIT(7) #define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) +#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) +#define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) @@ -1123,6 +1134,8 @@ #define RT_CTRL _MMIO(0xe530) #define DIS_NULL_QUERY REG_BIT(10) +#define STACKID_CTRL REG_GENMASK(6, 5) +#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2) #define EU_PERF_CNTL1 _MMIO(0xe558) #define EU_PERF_CNTL5 _MMIO(0xe55c) |