diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-04-29 13:10:32 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-06-30 20:39:18 +0300 |
| commit | 42ae1f88feacc8643bc56dcfa55e0722967e424f (patch) | |
| tree | bfb9e389be9d34cab55327493e0e7a984a52faf8 /drivers/gpu/drm/i915/display/intel_fbc.c | |
| parent | a68ce21ba0c44f5504e1e5bb0e5151b239540dc5 (diff) | |
| download | linux-42ae1f88feacc8643bc56dcfa55e0722967e424f.tar.bz2 | |
drm/i915/fbc: Reduce fbc1 compression interval to 1 second
The default fbc1 compression interval we use is 500 frames. That
translates to over 8 seconds typically. That's rather excessive
so let's drop it to 1 second.
The hardware will not attempt recompression unless at least one
line has been modified, so a shorter compression interval should
not cause extra bandwidth use in the purely idle scenario. Of
course in the mostly idle case we are possibly going to recompress
a bit more.
Should really try to find some kind of sweet spot to minimize
the energy usage...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200429101034.8208-11-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_fbc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fbc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 09b424611548..69a0682ddb6a 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -698,8 +698,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->fb.stride = fb->pitches[0]; cache->fb.modifier = fb->modifier; - /* This value was pulled out of someone's hat */ - cache->interval = 500; + /* FBC1 compression interval: arbitrary choice of 1 second */ + cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); cache->fence_y_offset = intel_plane_fence_y_offset(plane_state); |