diff options
| author | Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> | 2022-09-13 11:33:41 -0700 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2022-09-14 15:05:49 -0700 |
| commit | 4aaa1a98331c9f9fd31f4b80b913c8f0c556c90a (patch) | |
| tree | 80ac7217aaddf7ff380dd8e12994902717ad86d1 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | 851d635a0bf2a741d0e57889b5defcdf9ebfc70e (diff) | |
| download | linux-4aaa1a98331c9f9fd31f4b80b913c8f0c556c90a.tar.bz2 | |
drm/i915/mtl: Update CHICKEN_TRANS* register addresses
In Display version 14, Transcoder Chicken Registers have updated address.
This patch performs checks to use the right register when required.
v2: Omit display version check in i915_reg.h(Jani)
v3:
- Remove extra whitespace introduced
- Fix reg definitions for MTL_CHICKEN_TRANS(MattR)
Bspec: 34387, 50054
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220913183341.908028-6-radhakrishna.sripada@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 5adfd226d6c4..03604a37931c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -565,7 +565,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base, drm_atomic_get_mst_payload_state(mst_state, connector->port)); - if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) + if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable) + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0, + FECSTALL_DIS_DPTSTREAM_DPTTG); + else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, FECSTALL_DIS_DPTSTREAM_DPTTG); |