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authorImre Deak <imre.deak@intel.com>2022-09-01 23:03:37 -0700
committerRadhakrishna Sripada <radhakrishna.sripada@intel.com>2022-09-12 15:22:04 -0700
commit40151be79668232187b1ba7e00983be76a7f5845 (patch)
tree0f43daadb231aab36cfc42b031b75febfc58da3c /drivers/gpu/drm/i915/display/intel_dp_aux.c
parente5d464d02f0681c4677c0bb5f6c0a70c8be78ab6 (diff)
downloadlinux-40151be79668232187b1ba7e00983be76a7f5845.tar.bz2
drm/i915/mtl: Add display power wells
Add support for display power wells on MTL. The differences from XE_LPD: - The AUX HW block is moved to the PICA block, where the registers are on an always-on power well and the functionality needs to be powered on/off via the AUX_CH_CTL register: [1], [2] - The DDI IO power on/off programming sequence is moved to the PHY PLL enable/disable sequence. [3], [4], [5] Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450 v2: - Update the comment in aux power well enable - Reuse the noop sync fn for aux sync. - Use REG_BIT for new register bit definitions Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220902060342.151824-7-radhakrishna.sripada@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_aux.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dp_aux.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index f2ad1d09ab43..98bd33645b43 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -150,6 +150,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
u32 unused)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
u32 ret;
/*
@@ -170,6 +171,13 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
if (intel_tc_port_in_tbt_alt_mode(dig_port))
ret |= DP_AUX_CH_CTL_TBT_IO;
+ /*
+ * Power request bit is already set during aux power well enable.
+ * Preserve the bit across aux transactions.
+ */
+ if (DISPLAY_VER(i915) >= 14)
+ ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST;
+
return ret;
}