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authorAnshuman Gupta <anshuman.gupta@intel.com>2019-10-07 15:16:07 +0530
committerImre Deak <imre.deak@intel.com>2019-10-08 11:05:25 +0300
commite45e0003f60d3e9d62d9bb42d72efbbada7132bc (patch)
tree736e153cc0fe8591b5fbfcc7466e116e7ee580e0 /drivers/gpu/drm/i915/display/intel_display_power.c
parenta4c969d107a66369e6b8bf6b2fa28ca01723133b (diff)
downloadlinux-e45e0003f60d3e9d62d9bb42d72efbbada7132bc.tar.bz2
drm/i915/tgl: Add DC3CO required register and bits
Adding following definition to i915_reg.h 1. DC_STATE_EN register DC3CO bit fields and masks. DC3CO enable bit will be used by driver to make DC3CO ready for DMC f/w and status bit will be used as DC3CO entry status. 2. Transcoder EXITLINE register and its bit fields and mask. Transcoder EXITLINE enable bit represents PSR2 idle frame reset should be applied at exit line and exitlines mask represent required number of scanlines at which DC3CO exit happens. B.Specs:49196 v1: Use of REG_BIT and using extra space for EXITLINE_ macro definition. [Animesh] v2: Grouping EXITLINE reg bits with EXITLINE(trans) define, no functional change. [Ville] Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191007094607.2111-1-anshuman.gupta@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_power.c')
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