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| author | Manasi Navare <manasi.d.navare@intel.com> | 2021-01-22 15:26:42 -0800 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2021-01-25 15:23:18 -0800 |
| commit | 1639406a31c23ca07a2b8a9b45d1c400debda9e9 (patch) | |
| tree | 8c841e25cdc6659fe5989d2f7d5af5f4339079c5 /drivers/gpu/drm/i915/display/intel_display.c | |
| parent | f065123299f5af97e9a41567560413d453279d5e (diff) | |
| download | linux-1639406a31c23ca07a2b8a9b45d1c400debda9e9.tar.bz2 | |
drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.
v2:
* ACtually set the dpcd msa ignore bit (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-13-manasi.d.navare@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display.c')
0 files changed, 0 insertions, 0 deletions