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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-01-28 12:37:44 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-02-01 11:14:40 +0200 |
| commit | be0c94ee215043c0a5cdbffc5c45b5073054e125 (patch) | |
| tree | fcf3095bb48de407630678cee85bacdea3bf03b4 /drivers/gpu/drm/i915/display/intel_ddi.c | |
| parent | cc954cfa6fe47579aa8eceaed00677feda0a95b6 (diff) | |
| download | linux-be0c94ee215043c0a5cdbffc5c45b5073054e125.tar.bz2 | |
drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variants
Make things a bit more explicit by splitting
intel_cpu_transcoder_set_m_n() into separate variants for M1/N1 vs.
M2/N2. Makes the DRRS M/N programming at least more obvious.
Note that for the MST and DRRS cases we don't need to call the
M2/N2 variant at all since the transcoders that support those
do not have the M2/N2 registers.
Same could be said for i9xx_crtc_enable() but I want to do a
higher level code sharing between that valleyview_crtc_enable()
later in which case we do need the M2/N2 variant. This is also
why I keep the transcoder_has_m2_n2() in intel_cpu_transcoder_set_m2_n2()
so the caller doesn't have necessarily care what the chosen
transcoder supports.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_ddi.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2eb868eaab8f..dead4b72719f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2510,9 +2510,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { intel_ddi_set_dp_msa(crtc_state, conn_state); - intel_cpu_transcoder_set_m_n(crtc_state, - &crtc_state->dp_m_n, - &crtc_state->dp_m2_n2); + intel_cpu_transcoder_set_m1_n1(crtc_state, + &crtc_state->dp_m_n); + intel_cpu_transcoder_set_m2_n2(crtc_state, + &crtc_state->dp_m2_n2); } } |