diff options
| author | Stefan Agner <stefan@agner.ch> | 2015-11-17 18:05:25 -0800 |
|---|---|---|
| committer | Stefan Agner <stefan@agner.ch> | 2016-02-25 16:13:16 -0800 |
| commit | efb8b49196c0cb0723024182e04072abaec96cdf (patch) | |
| tree | 279c06460c0b24a8edefc58aa34ac609f5721a66 /drivers/gpu/drm/fsl-dcu | |
| parent | a36c9867d44718487262643cdefd12a386841b41 (diff) | |
| download | linux-efb8b49196c0cb0723024182e04072abaec96cdf.tar.bz2 | |
drm/fsl-dcu: specify volatile registers
Since we are using cached registers, we need to specify volatile
registers explicitly to avoid reading their value from the cache.
This allows to read the correct interrupt status in fsl_dcu_drm_irq
and clear the asserted bits only.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'drivers/gpu/drm/fsl-dcu')
| -rw-r--r-- | drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index 9648b7f9a31c..b4e33e3e0250 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -28,11 +28,21 @@ #include "fsl_dcu_drm_crtc.h" #include "fsl_dcu_drm_drv.h" +static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg) +{ + if (reg == DCU_INT_STATUS || reg == DCU_UPDATE_MODE) + return true; + + return false; +} + static const struct regmap_config fsl_dcu_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .cache_type = REGCACHE_RBTREE, + + .volatile_reg = fsl_dcu_drm_is_volatile_reg, }; static int fsl_dcu_drm_irq_init(struct drm_device *dev) @@ -125,7 +135,7 @@ static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg) if (int_status & DCU_INT_STATUS_VBLANK) drm_handle_vblank(dev, 0); - ret = regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0xffffffff); + ret = regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status); if (ret) dev_err(dev->dev, "set DCU_INT_STATUS failed\n"); ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, |