diff options
| author | Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> | 2022-08-31 11:26:51 +0300 |
|---|---|---|
| committer | Robert Foss <robert.foss@linaro.org> | 2022-09-02 18:17:57 +0200 |
| commit | 3fc307dcec8b9aeecae8c1bf2c97f770805daf4e (patch) | |
| tree | 356db5215a4075b899ba11d1595858f8c118a14f /drivers/gpu/drm/bridge | |
| parent | e06a46087d8bbde7ca31361789edfe026b08fdce (diff) | |
| download | linux-3fc307dcec8b9aeecae8c1bf2c97f770805daf4e.tar.bz2 | |
drm/bridge: ti-sn65dsi86: Reject modes with too large blanking
The front and back porch registers are 8 bits, and pulse width registers
are 15 bits, so reject any modes with larger periods.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220831082653.20449-2-tomi.valkeinen@ideasonboard.com
Diffstat (limited to 'drivers/gpu/drm/bridge')
| -rw-r--r-- | drivers/gpu/drm/bridge/ti-sn65dsi86.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 90bbabde1595..09d3c65fa2ba 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -747,6 +747,29 @@ ti_sn_bridge_mode_valid(struct drm_bridge *bridge, if (mode->clock > 594000) return MODE_CLOCK_HIGH; + /* + * The front and back porch registers are 8 bits, and pulse width + * registers are 15 bits, so reject any modes with larger periods. + */ + + if ((mode->hsync_start - mode->hdisplay) > 0xff) + return MODE_HBLANK_WIDE; + + if ((mode->vsync_start - mode->vdisplay) > 0xff) + return MODE_VBLANK_WIDE; + + if ((mode->hsync_end - mode->hsync_start) > 0x7fff) + return MODE_HSYNC_WIDE; + + if ((mode->vsync_end - mode->vsync_start) > 0x7fff) + return MODE_VSYNC_WIDE; + + if ((mode->htotal - mode->hsync_end) > 0xff) + return MODE_HBLANK_WIDE; + + if ((mode->vtotal - mode->vsync_end) > 0xff) + return MODE_VBLANK_WIDE; + return MODE_OK; } |