drm/amd/display: update dcn register headers

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 11 insertions, 8 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
index f14e208dbf1c..69db441e78c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
@@ -87,7 +87,6 @@
 	SRI(CM_DGAM_CONTROL, CM, id), \
 	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
 	SRI(DPP_CONTROL, DPP_TOP, id), \
-	SRI(CURSOR_SETTINS, HUBPREQ, id), \
 	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
 	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
 	SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
@@ -95,6 +94,7 @@
 
 #define IPP_REG_LIST_DCN10(id) \
 	IPP_REG_LIST_DCN(id), \
+	SRI(CURSOR_SETTINS, HUBPREQ, id), \
 	SRI(CM_IGAM_CONTROL, CM, id), \
 	SRI(CM_COMA_C11_C12, CM, id), \
 	SRI(CM_COMA_C13_C14, CM, id), \
@@ -240,8 +240,6 @@
 	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \
 	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
 	IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
-	IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
-	IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
 	IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
 	IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
 	IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
@@ -250,6 +248,8 @@
 
 #define IPP_MASK_SH_LIST_DCN10(mask_sh) \
 	IPP_MASK_SH_LIST_DCN(mask_sh),\
+	IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
+	IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
 	IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh), \
 	IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh), \
 	IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh), \
@@ -537,6 +537,7 @@ struct dcn10_ipp_registers {
 	uint32_t CM_IGAM_CONTROL;
 	uint32_t DPP_CONTROL;
 	uint32_t CURSOR_SETTINS;
+	uint32_t CURSOR_SETTINGS;
 	uint32_t CNVC_SURFACE_PIXEL_FORMAT;
 	uint32_t CURSOR0_CONTROL;
 	uint32_t CURSOR0_COLOR0;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index a0a1cef38d18..0f4d247c4237 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -75,7 +75,6 @@
 	SRI(BLANK_OFFSET_1, HUBPREQ, id),\
 	SRI(DST_DIMENSIONS, HUBPREQ, id),\
 	SRI(DST_AFTER_SCALER, HUBPREQ, id),\
-	SRI(PREFETCH_SETTINS, HUBPREQ, id),\
 	SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
 	SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
 	SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
@@ -86,7 +85,6 @@
 	SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
 	SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
 	SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
-	SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
 	SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
 	SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
 	SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
@@ -140,6 +138,8 @@
 
 #define MI_REG_LIST_DCN10(id)\
 	MI_REG_LIST_DCN(id),\
+	SRI(PREFETCH_SETTINS, HUBPREQ, id),\
+	SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
 	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
 	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
 	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
@@ -206,6 +206,7 @@ struct dcn_mi_registers {
 	uint32_t DST_DIMENSIONS;
 	uint32_t DST_AFTER_SCALER;
 	uint32_t PREFETCH_SETTINS;
+	uint32_t PREFETCH_SETTINGS;
 	uint32_t VBLANK_PARAMETERS_0;
 	uint32_t REF_FREQ_TO_PIX_FREQ;
 	uint32_t VBLANK_PARAMETERS_1;
@@ -217,6 +218,7 @@ struct dcn_mi_registers {
 	uint32_t PER_LINE_DELIVERY_PRE;
 	uint32_t PER_LINE_DELIVERY;
 	uint32_t PREFETCH_SETTINS_C;
+	uint32_t PREFETCH_SETTINGS_C;
 	uint32_t VBLANK_PARAMETERS_2;
 	uint32_t VBLANK_PARAMETERS_4;
 	uint32_t NOM_PARAMETERS_2;
@@ -388,8 +390,6 @@ struct dcn_mi_registers {
 	MI_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
 	MI_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
 	MI_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
-	MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
-	MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
 	MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
 	MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
 	MI_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
@@ -403,7 +403,6 @@ struct dcn_mi_registers {
 	MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
 	MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
 	MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
-	MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
 	MI_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
 	MI_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
 	MI_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
@@ -429,6 +428,9 @@ struct dcn_mi_registers {
 
 #define MI_MASK_SH_LIST_DCN10(mask_sh)\
 	MI_MASK_SH_LIST_DCN(mask_sh),\
+	MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
+	MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
+	MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
 	MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
 	MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
 	MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\