diff options
| author | Michael Strauss <michael.strauss@amd.com> | 2022-11-17 10:40:46 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-12-06 10:16:02 -0500 |
| commit | 54e9ea3d5dc8f215abe53c355ddc70c18e0d3329 (patch) | |
| tree | 0498e81916ae18bd521e896f95b10b5ab8480dd9 /drivers/gpu/drm/amd | |
| parent | 39173f248a5416286c7f42961b717ee39e0e0d1f (diff) | |
| download | linux-54e9ea3d5dc8f215abe53c355ddc70c18e0d3329.tar.bz2 | |
drm/amd/display: Fix DCN2.1 default DSC clocks
[WHY]
Low dscclk in high vlevels blocks some DSC modes.
[HOW]
Update dscclk to 1/3 of dispclk.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index c4eca10587a6..c26da3bb2892 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -565,7 +565,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { .dppclk_mhz = 847.06, .phyclk_mhz = 810.0, .socclk_mhz = 953.0, - .dscclk_mhz = 489.0, + .dscclk_mhz = 300.0, .dram_speed_mts = 2400.0, }, { @@ -576,7 +576,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { .dppclk_mhz = 960.00, .phyclk_mhz = 810.0, .socclk_mhz = 278.0, - .dscclk_mhz = 287.67, + .dscclk_mhz = 342.86, .dram_speed_mts = 2666.0, }, { @@ -587,7 +587,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { .dppclk_mhz = 1028.57, .phyclk_mhz = 810.0, .socclk_mhz = 715.0, - .dscclk_mhz = 318.334, + .dscclk_mhz = 369.23, .dram_speed_mts = 3200.0, }, { |