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| author | Kevin Wang <kevin1.wang@amd.com> | 2019-03-04 19:50:02 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-21 18:59:25 -0500 |
| commit | 940680c3b48a5d90896e638cb6ec3bf1a2cebcfa (patch) | |
| tree | cf9c1b902442f5591851b9b5a11719cd2b264c44 /drivers/gpu/drm/amd/powerplay/vega20_ppt.c | |
| parent | 1e87e0124ba413b751ee03b09f5520e778982b58 (diff) | |
| download | linux-940680c3b48a5d90896e638cb6ec3bf1a2cebcfa.tar.bz2 | |
drm/amd/powerplay: move the funciton of conv_profile_to_workload to asic file
the function of conv_profile_to_workload is asic related function,
so move them into vega20_ppt file
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/vega20_ppt.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index 62497ad66a39..3243928b6ee2 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -1496,6 +1496,37 @@ static int vega20_get_od_percentage(struct smu_context *smu, return value; } +static int vega20_conv_profile_to_workload(struct smu_context *smu, int power_profile) +{ + int pplib_workload = 0; + + switch (power_profile) { + case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT: + pplib_workload = WORKLOAD_DEFAULT_BIT; + break; + case PP_SMC_POWER_PROFILE_FULLSCREEN3D: + pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; + break; + case PP_SMC_POWER_PROFILE_POWERSAVING: + pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT; + break; + case PP_SMC_POWER_PROFILE_VIDEO: + pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; + break; + case PP_SMC_POWER_PROFILE_VR: + pplib_workload = WORKLOAD_PPLIB_VR_BIT; + break; + case PP_SMC_POWER_PROFILE_COMPUTE: + pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT; + break; + case PP_SMC_POWER_PROFILE_CUSTOM: + pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT; + break; + } + + return pplib_workload; +} + static int vega20_get_profiling_clk_mask(struct smu_context *smu, enum amd_dpm_forced_level level, @@ -2541,6 +2572,7 @@ static const struct pptable_funcs vega20_ppt_funcs = { .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency, .set_default_od8_settings = vega20_set_default_od8_setttings, .get_od_percentage = vega20_get_od_percentage, + .conv_profile_to_workload = vega20_conv_profile_to_workload, .get_performance_level = vega20_get_performance_level, .force_performance_level = vega20_force_performance_level, .update_specified_od8_value = vega20_update_specified_od8_value, |