diff options
| author | Wenhui Sheng <Wenhui.Sheng@amd.com> | 2020-07-10 17:39:24 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-15 12:41:32 -0400 |
| commit | ea8139d8d59bd6f014b317e7423345169a56fe49 (patch) | |
| tree | 5bf10243713474fab8ad722bcfccaacc22c027d8 /drivers/gpu/drm/amd/powerplay/smu_v11_0.c | |
| parent | a4497974ed339985fa89fabde9d5f6038bf1a59e (diff) | |
| download | linux-ea8139d8d59bd6f014b317e7423345169a56fe49.tar.bz2 | |
drm/amd/powerplay: add SMU mode1 reset
From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset
is support, driver sends PPSMC_MSG_Mode1Reset message
to PM FW could trigger this reset.
v2: add mode1 reset dpm interface
v3: change maro name
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/smu_v11_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index ba5e60b71c07..6b492a4dfb8e 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -63,6 +63,8 @@ MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin"); #define SMU11_VOLTAGE_SCALE 4 +#define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms + static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu, uint16_t msg) { @@ -1694,6 +1696,17 @@ int smu_v11_0_baco_exit(struct smu_context *smu) return ret; } +int smu_v11_0_mode1_reset(struct smu_context *smu) +{ + int ret = 0; + + ret = smu_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); + if (!ret) + msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS); + + return ret; +} + int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) { |