diff options
| author | Kevin Wang <kevin1.wang@amd.com> | 2019-05-16 15:06:25 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-21 18:59:31 -0500 |
| commit | eefa5e2b3030585ffb0e4afaf26ae5f28b3f9f8e (patch) | |
| tree | 40048b42b8533e24522ca2da19c0dc597c935190 /drivers/gpu/drm/amd/powerplay/navi10_ppt.c | |
| parent | d8ceb192cb8e1c1daa71242399ece5dba7cd3cf2 (diff) | |
| download | linux-eefa5e2b3030585ffb0e4afaf26ae5f28b3f9f8e.tar.bz2 | |
drm/amd/powerplay: enable uclk dpm default on navi10
enable uclk (mclk) dpm by default on navi10
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/navi10_ppt.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index afdf5238d1c3..9463eff8d907 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -314,6 +314,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | FEATURE_MASK(FEATURE_DPM_LINK_BIT) + | FEATURE_MASK(FEATURE_DPM_UCLK_BIT) + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) + | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT) | FEATURE_MASK(FEATURE_GFX_ULV_BIT) | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) @@ -332,11 +335,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) | FEATURE_MASK(FEATURE_ACDC_BIT); - if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); - if (adev->pm.pp_feature & PP_GFXOFF_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT) | FEATURE_MASK(FEATURE_GFXOFF_BIT); @@ -350,7 +348,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, if ((adev->asic_type == CHIP_NAVI10) && (adev->rev_id == 0)) { *(uint64_t *)feature_mask &= - ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); + ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT) + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) + | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT)); *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); } |