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| author | Kevin Wang <kevin1.wang@amd.com> | 2019-07-05 15:58:46 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-05 15:59:08 -0500 |
| commit | 767acabdac81ded97e8f6930bc2dabff8db1638c (patch) | |
| tree | 5c75c09479d3c67a04472d645724e08fc8efd17d /drivers/gpu/drm/amd/powerplay/inc | |
| parent | e3000669a7b4b26383fad06af8f736ad3b5d161e (diff) | |
| download | linux-767acabdac81ded97e8f6930bc2dabff8db1638c.tar.bz2 | |
drm/amd/powerplay: add baco smu reset function for smu11
add baco reset support for smu11.
it can help gpu do asic reset when gpu recovery.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 26 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 |
2 files changed, 34 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index 2818df46481c..c97324ef7db2 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -241,6 +241,7 @@ enum smu_message_type SMU_MSG_PowerUpJpeg, SMU_MSG_PowerDownJpeg, SMU_MSG_BacoAudioD3PME, + SMU_MSG_ArmD3, SMU_MSG_MAX_COUNT, }; @@ -489,6 +490,19 @@ struct mclock_latency_table { struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; }; +enum smu_baco_state +{ + SMU_BACO_STATE_ENTER = 0, + SMU_BACO_STATE_EXIT, +}; + +struct smu_baco_context +{ + struct mutex mutex; + uint32_t state; + bool platform_support; +}; + #define WORKLOAD_POLICY_MAX 7 struct smu_context { @@ -505,6 +519,7 @@ struct smu_context struct smu_power_context smu_power; struct smu_feature smu_feature; struct amd_pp_display_configuration *display_config; + struct smu_baco_context smu_baco; void *od_settings; uint32_t pstate_sclk; @@ -680,6 +695,11 @@ struct smu_funcs int (*register_irq_handler)(struct smu_context *smu); int (*set_azalia_d3_pme)(struct smu_context *smu); int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); + bool (*baco_is_support)(struct smu_context *smu); + enum smu_baco_state (*baco_get_state)(struct smu_context *smu); + int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); + int (*baco_reset)(struct smu_context *smu); + }; #define smu_init_microcode(smu) \ @@ -892,6 +912,12 @@ struct smu_funcs ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0) #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \ ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0) +#define smu_baco_is_support(smu) \ + ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false) +#define smu_baco_get_state(smu, state) \ + ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0) +#define smu_baco_reset(smu) \ + ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0) extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, uint16_t *size, uint8_t *frev, uint8_t *crev, diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h index d93cd76269b4..2fff4b16cb4e 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h @@ -105,6 +105,14 @@ struct smu_11_0_power_context { enum smu_11_0_power_state power_state; }; +enum smu_v11_0_baco_seq { + BACO_SEQ_BACO = 0, + BACO_SEQ_MSR, + BACO_SEQ_BAMACO, + BACO_SEQ_ULPS, + BACO_SEQ_COUNT, +}; + void smu_v11_0_set_smu_funcs(struct smu_context *smu); #endif |