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authorEvan Quan <evan.quan@amd.com>2021-03-17 12:10:15 +0800
committerAlex Deucher <alexander.deucher@amd.com>2021-04-09 16:37:53 -0400
commit1689fca0d62aa7a685363999f9fc380c0666d955 (patch)
treecb9601ff0840e97aa558e80eb06ef399ed324dc6 /drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
parent50ca25228e8a0cc4eca531cdac4c9ece1e7bed68 (diff)
downloadlinux-1689fca0d62aa7a685363999f9fc380c0666d955.tar.bz2
drm/amd/pm: fix Navi1x runtime resume failure V2
The RLC was put into a wrong state on runtime suspend. Thus the RLC autoload will fail on the succeeding runtime resume. By adding an intermediate PPSMC_MSG_PrepareMp1ForUnload(some GC hard reset involved, designed for PnP), we can bring RLC back into the desired state. V2: integrate INTERRUPTS_ENABLED flag clearing into current mp1 state set routines Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h')
-rw-r--r--drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 25d5f03aaa67..2edb634bc1c6 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -807,6 +807,13 @@ struct pptable_funcs {
int (*check_fw_status)(struct smu_context *smu);
/**
+ * @set_mp1_state: put SMU into a correct state for comming
+ * resume from runpm or gpu reset.
+ */
+ int (*set_mp1_state)(struct smu_context *smu,
+ enum pp_mp1_state mp1_state);
+
+ /**
* @setup_pptable: Initialize the power play table and populate it with
* default values.
*/