diff options
| author | Tom St Denis <tom.stdenis@amd.com> | 2016-11-07 14:06:01 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-11-11 10:21:08 -0500 |
| commit | 5e2e2119955a9f18beccd6603bdd255dad18eb15 (patch) | |
| tree | e479811526eddd1eb8fc43399e11e53a42132ed6 /drivers/gpu/drm/amd/include/asic_reg/gca | |
| parent | de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33 (diff) | |
| download | linux-5e2e2119955a9f18beccd6603bdd255dad18eb15.tar.bz2 | |
drm/amd/amdgpu: add SI defines/registers
Add missing gca MMIO registers and defines necessary for the
next patch which re-works a lot of gfx v6 to use the new SI
headers.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/gca')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h index b2829d0490cc..c75aee25619e 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h @@ -1757,4 +1757,28 @@ #define mmVGT_VTX_CNT_EN 0xA2AE #define mmVGT_VTX_VECT_EJECT_REG 0x222C +/* manually added from old sid.h */ +#define mmCB_PERFCOUNTER0_SELECT0 0x2688 +#define mmCB_PERFCOUNTER1_SELECT0 0x268A +#define mmCB_PERFCOUNTER1_SELECT1 0x268B +#define mmCB_PERFCOUNTER2_SELECT0 0x268C +#define mmCB_PERFCOUNTER2_SELECT1 0x268D +#define mmCB_PERFCOUNTER3_SELECT0 0x268E +#define mmCB_PERFCOUNTER3_SELECT1 0x268F +#define mmCP_COHER_CNTL2 0x217A +#define mmCP_DEBUG 0x307F +#define mmRLC_SERDES_MASTER_BUSY_0 0x3119 +#define mmRLC_SERDES_MASTER_BUSY_1 0x311A +#define mmRLC_RL_BASE 0x30C1 +#define mmRLC_RL_SIZE 0x30C2 +#define mmRLC_UCODE_ADDR 0x30CB +#define mmRLC_UCODE_DATA 0x30CC +#define mmRLC_GCPM_GENERAL_3 0x311E +#define mmRLC_SERDES_WR_MASTER_MASK_0 0x3115 +#define mmRLC_SERDES_WR_MASTER_MASK_1 0x3116 +#define mmRLC_TTOP_D 0x3105 +#define mmRLC_CLEAR_STATE_RESTORE_BASE 0x30C8 +#define mmRLC_PG_AO_CU_MASK 0x310B +#define mmSPI_STATIC_THREAD_MGMT_3 0x243A + #endif |