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| author | Mauro Rossi <issor.oruam@gmail.com> | 2019-05-26 17:33:45 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-27 16:46:05 -0400 |
| commit | 55e56389bdecc4f08524a6ae81940b13f986e125 (patch) | |
| tree | 2d443ecd9eaad086e517207a0614f7a381a97ccc /drivers/gpu/drm/amd/include/amd_pcie_helpers.h | |
| parent | 61bf32937bdd05fdf74292460d56936d63beaba5 (diff) | |
| download | linux-55e56389bdecc4f08524a6ae81940b13f986e125.tar.bz2 | |
drm/amd/display: amdgpu_dm: add SI support (v4)
[Why]
amdgpu_dm.c requires changes for SI chipsets init and irq handlers registration
[How]
SI support: load_dmcu_fw(), amdgpu_dm_initialize_drm_device(), dm_early_init()
Add DCE6 specific dce60_register_irq_handlers() function
(v1) NOTE: As per Kaveri and older amdgpu.dc=1 kernel cmdline is required
(v2) fix for bc011f9 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence")
remove CHIP_HAINAN support since it does not have physical DCE6 module
(v3) fix vblank irq support for DCE6 using ad hoc dce60_register_irq_handlers()
replicating for vblank irq the behavior of dce110_register_irq_handlers()
as per commit b57de80 ("drm/amd/display: Register on VLBLANK ISR.")
(v4) updated due to following kernel 5.2 commit:
b2fddb13 ("drm/amd/display: Drop underlay plane support")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/amd_pcie_helpers.h')
0 files changed, 0 insertions, 0 deletions