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authorAhmad Othman <ahmad.othman@amd.com>2019-08-01 15:05:27 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-08-23 11:41:58 -0500
commita9f54ce3c6032361d2b69910114b6e8baf9bdf49 (patch)
tree90f01e1ba2a44f82e4bb16a6d1528360066e88f7 /drivers/gpu/drm/amd/display/modules/info_packet
parent37fe34d243265f792fe2d122bde6e645ad4c1490 (diff)
downloadlinux-a9f54ce3c6032361d2b69910114b6e8baf9bdf49.tar.bz2
drm/amd/display: Refactoring VTEM
[Why] Video Timing Extended Metadata packet (VTEM) is not specific to freesync. So move it out of freesync module [How] - Moved VTEM from freesync module to info_packet module - Created new structure for VTEM parameters that can be used for VRR and FVA Signed-off-by: Ahmad Othman <ahmad.othman@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Ahmad Othman <Ahmad.Othman@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/info_packet')
-rw-r--r--drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c88
1 files changed, 88 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
index bc13c552797f..5f4b98df3d92 100644
--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
@@ -27,9 +27,78 @@
#include "core_types.h"
#include "dc_types.h"
#include "mod_shared.h"
+#include "mod_freesync.h"
+#include "dc.h"
#define HDMI_INFOFRAME_TYPE_VENDOR 0x81
+// VTEM Byte Offset
+#define VTEM_PB0 0
+#define VTEM_PB1 1
+#define VTEM_PB2 2
+#define VTEM_PB3 3
+#define VTEM_PB4 4
+#define VTEM_PB5 5
+#define VTEM_PB6 6
+
+#define VTEM_MD0 7
+#define VTEM_MD1 8
+#define VTEM_MD2 9
+#define VTEM_MD3 10
+
+
+// VTEM Byte Masks
+//PB0
+#define MASK_VTEM_PB0__RESERVED0 0x01
+#define MASK_VTEM_PB0__SYNC 0x02
+#define MASK_VTEM_PB0__VFR 0x04
+#define MASK_VTEM_PB0__AFR 0x08
+#define MASK_VTEM_PB0__DS_TYPE 0x30
+ //0: Periodic pseudo-static EM Data Set
+ //1: Periodic dynamic EM Data Set
+ //2: Unique EM Data Set
+ //3: Reserved
+#define MASK_VTEM_PB0__END 0x40
+#define MASK_VTEM_PB0__NEW 0x80
+
+//PB1
+#define MASK_VTEM_PB1__RESERVED1 0xFF
+
+//PB2
+#define MASK_VTEM_PB2__ORGANIZATION_ID 0xFF
+ //0: This is a Vendor Specific EM Data Set
+ //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
+ //2: This EM Data Set is defined by CTA-861-G
+ //3: This EM Data Set is defined by VESA
+//PB3
+#define MASK_VTEM_PB3__DATA_SET_TAG_MSB 0xFF
+//PB4
+#define MASK_VTEM_PB4__DATA_SET_TAG_LSB 0xFF
+//PB5
+#define MASK_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
+//PB6
+#define MASK_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
+
+
+
+//PB7-27 (20 bytes):
+//PB7 = MD0
+#define MASK_VTEM_MD0__VRR_EN 0x01
+#define MASK_VTEM_MD0__M_CONST 0x02
+#define MASK_VTEM_MD0__RESERVED2 0x0C
+#define MASK_VTEM_MD0__FVA_FACTOR_M1 0xF0
+
+//MD1
+#define MASK_VTEM_MD1__BASE_VFRONT 0xFF
+
+//MD2
+#define MASK_VTEM_MD2__BASE_REFRESH_RATE_98 0x03
+#define MASK_VTEM_MD2__RB 0x04
+#define MASK_VTEM_MD2__RESERVED3 0xF8
+
+//MD3
+#define MASK_VTEM_MD3__BASE_REFRESH_RATE_07 0xFF
+
enum ColorimetryRGBDP {
ColorimetryRGB_DP_sRGB = 0,
ColorimetryRGB_DP_AdobeRGB = 3,
@@ -45,6 +114,25 @@ enum ColorimetryYCCDP {
ColorimetryYCC_DP_ITU2020YCbCr = 7,
};
+void setFieldWithMask(unsigned char *dest, unsigned int mask, unsigned int value)
+{
+ unsigned int shift = 0;
+
+ if (!mask || !dest)
+ return;
+
+ while (!((mask >> shift) & 1))
+ shift++;
+
+ //reset
+ *dest = *dest & ~mask;
+ //set
+ //dont let value span past mask
+ value = value & (mask >> shift);
+ //insert value
+ *dest = *dest | (value << shift);
+}
+
void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
struct dc_info_packet *info_packet)
{