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| author | Ian Chen <ian.chen@amd.com> | 2021-05-10 12:17:26 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-14 21:38:40 -0400 |
| commit | a34136a3b3526369e1b3e678590e3760e7653f0f (patch) | |
| tree | 3f4c5569287bac050a9dcf6dd14a40699cce993a /drivers/gpu/drm/amd/display/modules/freesync | |
| parent | f69e98a91a01fd7c5755dd710e94a17d6e9f583f (diff) | |
| download | linux-a34136a3b3526369e1b3e678590e3760e7653f0f.tar.bz2 | |
drm/amd/display: DAL ACR, dc part, fix missing dcn30
[Why]
- missing in dcn30 function
- Fix a divide by 0 when ACR trigger
[How]
- Add IS_SMU_TIMEOUT() to dcn30_smu_send_msg_with_param
- Add zero check in dcn20_update_clocks_update_dentist
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync')
0 files changed, 0 insertions, 0 deletions