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| author | Aric Cyr <aric.cyr@amd.com> | 2020-07-27 21:21:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-08-10 17:26:52 -0400 |
| commit | 5396fa590df764775e83c9014330bc4112a75f63 (patch) | |
| tree | 8db9dbdcc164e0d182cb8f61ecd0c0b61e2be279 /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | fe04afad4ee144557fbf7196c5746cfe57fbdf47 (diff) | |
| download | linux-5396fa590df764775e83c9014330bc4112a75f63.tar.bz2 | |
drm/amd/display: Fix incorrect backlight register offset for DCN
[Why]
Typo in backlight refactor inctroduced wrong register offset.
[How]
Change DCE to DCN register map for PWRSEQ_REF_DIV
Cc: stable@vger.kernel.org
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
0 files changed, 0 insertions, 0 deletions